2007 50th Midwest Symposium on Circuits and Systems最新文献_第8页

Designing CMOS hardware processor for vehicle tracking 设计用于车辆跟踪的CMOS硬件处理器

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488796

Hua Tang, T. Kwon, Yi Zheng, Hairong Chang

引用次数: 1

A low power IC to enable optical communications in a robotic swarm 一种低功耗集成电路，可在机器人群中实现光通信

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488702

O. Alonso, R. Casanova, A. Sanuy, A. Arbat, J. Canals, Á. Diéguez, J. Samitier

引用次数: 1

A robust pitch detection algorithm for speech signals in a practical noisy environment 一种在实际噪声环境下对语音信号进行鲁棒基音检测的算法

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488611

C. Shahnaz, W. Zhu, M. Ahmad

引用次数: 1

Design trade-offs for load/store buffers in embedded processing environments 在嵌入式处理环境中设计负载/存储缓冲区的权衡

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488819

Y. Kang, J. Draper

{"title":"Design trade-offs for load/store buffers in embedded processing environments","authors":"Y. Kang, J. Draper","doi":"10.1109/MWSCAS.2007.4488819","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488819","url":null,"abstract":"Memory latency is a critical issue for conventional high-speed computing platforms, and it is becoming a common problem in embedded and CMP (chip multiprocessing) systems as well. Conventional processors typically adopt caches and a load/store queue (LSQ) to address the processor-to-memory bottleneck. However, the conventional LSQ design, which has a large number of entries, is not appropriate for embedded systems due to its area and power hungry out-of- order speculation. A compact, low-power load/store buffer that also provides significant performance improvement is essential for such systems. In this paper, we propose an area-efficient wideword load/store buffer (WLSB) which supports both WideWord (256-bit) and scalar (32-bit) load/store instructions for a recently fabricated PIM (processing-in-memory) device. Given its small size, the 4 entry WLSB yields a 57.33% load hit rate on SPEC2K benchmarks. This result is 5.72% better as compared to a less area-efficient 32-entry fully associative scalar load/store buffer (SLSB). The WLSB was synthesized in IBM 90 nm technology, and the resulting implementation occupies less than a seventh of a square mm and is projected to run at 1.6 ns cycle time with 15.72 mW of dynamic power dissipation. This paper demonstrates how this very small-entry buffer can affect the load hit rate and quantifies the design trade-offs between wide small-entry and narrow large-entry buffers with respect to size, power, load hit ratio and clock speed. Although this WLSB has been specifically designed to benefit a PIM architecture, it is expected to be useful for other embedded processing platforms and CMPs due to emphasized area/power constraints.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129076283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low noise 13 GHz power efficient 16/17 prescaler with rail to rail output amplitude 低噪声13 GHz功率高效16/17预分频器，轨到轨输出幅度

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488621

E. Eschenko, M. S. Candidate, K. Entesari

{"title":"A low noise 13 GHz power efficient 16/17 prescaler with rail to rail output amplitude","authors":"E. Eschenko, M. S. Candidate, K. Entesari","doi":"10.1109/MWSCAS.2007.4488621","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488621","url":null,"abstract":"A state of the art 16/17 prescaler using current mode logic (CML) D-Flip Flops, CMOS inverters, and transmission gates for the .18mu TSMC process with a 1.8 V supply voltage is presented. The prescaler consists of a 4/5 synchronous core and a feedback loop which modulates the 4/5 core to produce a division ratio of 16/17. Instead of employing power hungry CML, the feedback circuit takes advantage of low power NOR and AND gates realized in transmission gate logic (TGL) to reduce the power consumption. To the best of our knowledge, this technique has never been used in a high frequency prescaler before. Additionally, this work will serve as a comprehensive description of the numerous considerations of prescaler design including explanation of gate-level design and transistor level optimization. Furthermore, digital circuit output is efficiently buffered with CMOS inverters for rail- to-rail operation, maximizing slew rate which minimizes phase noise. The simulated phase noise is -150 dBc/Hz @ 1 MHz and the input bandwidth is 2 GHz (11 GHz and 13 GHz). The power consumption of the entire prescaler is 18.5 mW. All of the above results were obtained from post-layout simulations. Circuit layout has been completed and sent for fabrication.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133650212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Precise free-running period synthesizer (FRPS) with process and temperature compensation 精确的自由运行周期合成器(FRPS)，具有过程和温度补偿

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488754

B. Pontikakis, F. Boyer, Y. Savaria, H. Bui

引用次数: 10

Delay and slew analysis of VLSI interconnects using difference model approach 差分模型法分析VLSI互连的时延和摆幅

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488792

J. Ravindra, M. Srinivas

{"title":"Delay and slew analysis of VLSI interconnects using difference model approach","authors":"J. Ravindra, M. Srinivas","doi":"10.1109/MWSCAS.2007.4488792","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488792","url":null,"abstract":"In high speed digital integrated circuits, inductive- coupling effects in interconnects can be significant and should be included for accurate delay-noise analysis. In this paper, an analytical framework to model delay and slew metrics in coupled RLC interconnects is presented. The proposed models are based on difference model approach which involves the dynamic part of system transfer function. The models are generic in nature and can be applied to symmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture delay and slew accurately. Over a large set of random test cases, the average error in delay and slew estimation is approximately 1.8% and 3.2% respectively. A key feature of the new model is that its derivation and form enables an insight into the inductively coupled noise-waveform. Due to its simplicity and physical nature, the proposed model can be applied to asymmetric transmission lines. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when capacitive and inductive coupling are considered together.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116176637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An advanced placement method for SoC floorplanning based on ACO algorithm 一种基于蚁群算法的SoC布局优化方法

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488757

Rong Luo, Peng Sun

引用次数: 1

CMOS integrated system for magnetic field monitoring and gradient measurement in MRI environment MRI环境下磁场监测与梯度测量的CMOS集成系统

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488543

V. Frick, J. Pascal, L. Hébrard, J. Blonde, J. Felblinger

引用次数: 10

SiP power management unit with embedded temperature sensor powered by piezoelectric vibration energy harvesting SiP电源管理单元，内置温度传感器，由压电振动能量收集供电

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488666

J. Colomer, P. Miribel, A. Saiz-Vela, J. Brufau, J. Maa, M. Puig-Vidal, J. Samitier

引用次数: 5