差分模型法分析VLSI互连的时延和摆幅

J. Ravindra, M. Srinivas
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引用次数: 0

摘要

在高速数字集成电路中,互连中的电感耦合效应可能是显著的,为了准确地分析延迟噪声,应该将其包括在内。本文提出了一种耦合RLC互连中时延和回转指标建模的分析框架。所提出的模型基于差分模型方法,涉及系统传递函数的动态部分。这些模型本质上是通用的,可以应用于攻击者和受害者线路的对称驱动和线路配置。将该模型与SPICE仿真进行了比较,结果表明该模型能够准确地捕获延迟和回转。在大量随机测试用例中,延迟和回转估计的平均误差分别约为1.8%和3.2%。新模型的一个关键特征是它的推导和形式使我们能够深入了解电感耦合噪声波形。由于该模型的简单性和物理性质,可以应用于非对称传输线。所得结果表明,当电容性和电感性耦合同时考虑时,常见的(电容性)噪声避免技术的性能会大不相同。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Delay and slew analysis of VLSI interconnects using difference model approach
In high speed digital integrated circuits, inductive- coupling effects in interconnects can be significant and should be included for accurate delay-noise analysis. In this paper, an analytical framework to model delay and slew metrics in coupled RLC interconnects is presented. The proposed models are based on difference model approach which involves the dynamic part of system transfer function. The models are generic in nature and can be applied to symmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture delay and slew accurately. Over a large set of random test cases, the average error in delay and slew estimation is approximately 1.8% and 3.2% respectively. A key feature of the new model is that its derivation and form enables an insight into the inductively coupled noise-waveform. Due to its simplicity and physical nature, the proposed model can be applied to asymmetric transmission lines. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when capacitive and inductive coupling are considered together.
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