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2007 50th Midwest Symposium on Circuits and Systems最新文献

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uSOL: A programming language for sensor networks 用于传感器网络的编程语言
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488690
Ramesh Bharadwaj, A. Biswas, J. James, S. Mukhopadhyay
{"title":"uSOL: A programming language for sensor networks","authors":"Ramesh Bharadwaj, A. Biswas, J. James, S. Mukhopadhyay","doi":"10.1109/MWSCAS.2007.4488690","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488690","url":null,"abstract":"We present an event-driven synchronous programming environment for coordinating and reorganizing sensor networks. More precisely, we present a synchronous programming language uSOL (secure operations language with uncertainty) that has capabilities of handling service invocations asynchronously, provides strong typing to ensure enforcement of information flow and security policies, has constructs for handling uncertainty, and has the ability to deal with failures (both benign and byzantine) of network components.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128470556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Continuous wavelet transform based source separation 基于连续小波变换的源分离
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488607
Lee-Pierre Belley, M. Gabrea, C. Gargour
{"title":"Continuous wavelet transform based source separation","authors":"Lee-Pierre Belley, M. Gabrea, C. Gargour","doi":"10.1109/MWSCAS.2007.4488607","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488607","url":null,"abstract":"Separation of convolutive mixtures of speech sources is considered in this paper. Several approaches have been reported in the literature using statistical methods as well as transforms such as the short time Fourier transform (STFT) and the Paquet wavelet transform (PWT). In this paper we propose a new source separation method based on the independent component analysis (ICA) and utilizing the continuous wavelet transform (CWT). The experimental results obtained by our method have been investigated and compared with those generated by other approaches.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A piecewise polynomial canonical representing function and its application to image edge processing 分段多项式正则表示函数及其在图像边缘处理中的应用
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488540
H. Okazaki, T. Shidara, Y. Okubo
{"title":"A piecewise polynomial canonical representing function and its application to image edge processing","authors":"H. Okazaki, T. Shidara, Y. Okubo","doi":"10.1109/MWSCAS.2007.4488540","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488540","url":null,"abstract":"The purpose of this paper is to present an explicit analytical representation for piecewise polynomial functions and to illustrate the application of this representation in cognitive processing in computer vision.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127093122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
From (integrated) circuits to systems of systems on chip in five decades: How did and will (IC) test technology keep up? 五十年来从集成电路到片上系统的系统:(IC)测试技术是如何以及将如何跟上?
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488835
A. Ivanov
{"title":"From (integrated) circuits to systems of systems on chip in five decades: How did and will (IC) test technology keep up?","authors":"A. Ivanov","doi":"10.1109/MWSCAS.2007.4488835","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488835","url":null,"abstract":"The past five decades amount to mind boggling progress in IC design and manufacturing technology. In this period, we have gone from the inception of ICs to now what literally amounts to the integration of systems of systems on chip. Whereas experts debate the continued evolution of ICs according to Moore's law beyond the next decade, the advent of the complex integration of multi-physics systems is just in its infancy and is predicted to grow exponentially in the coming years. Designing and manufacturing complex ICs is of course a feat in itself. Testing and testability has often been taken for granted as a necessary (not to say evil) requirement. But who wants of an IC that cannot be duly tested, to ensure quality and reliability, especially when deployed in life-critical applications? Test technology, along with design technology has had to make enormous and rapid progress over the past half-century. Here, we highlight some of the key elements of IC test technology. We briefly mention some directions and challenges and opportunities for test technology in the near future, especially as multi-physics integrated systems of systems continue to emerge and progress on the volume production curves.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125854032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A CMOS based microfluidic detector: Design, calibration and experimental results 一种基于CMOS的微流控探测器:设计、校准和实验结果
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488568
E. Ghafar-Zadeh, M. Sawan, M. Hajj-Hassan, M. A. Miled
{"title":"A CMOS based microfluidic detector: Design, calibration and experimental results","authors":"E. Ghafar-Zadeh, M. Sawan, M. Hajj-Hassan, M. A. Miled","doi":"10.1109/MWSCAS.2007.4488568","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488568","url":null,"abstract":"In this paper, we describe a 0.18 mum CMOS capacitive sensor for microfluidic applications. This sensor features an interface circuit, which is incorporated with a calibration circuitry. We present the design and thereafter simulation and experimental results in the support of discussed issues throughout this paper. The proposed interface circuit offers the advantage of low complexity as well as sub femto Farad resolution.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126399228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficient simulation of jitter tolerance for all-digital data recovery circuits 全数字数据恢复电路抖动容限的高效仿真
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488745
S.I. Ahmed, T. Kwasniewski
{"title":"Efficient simulation of jitter tolerance for all-digital data recovery circuits","authors":"S.I. Ahmed, T. Kwasniewski","doi":"10.1109/MWSCAS.2007.4488745","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488745","url":null,"abstract":"Clock and data recovery (CDR) Circuits are being increasingly marketed as intellectual property (IP) blocks for complex system-on-chip (SoC) and network-on-chip (NoC) products. As part of the mixed-signal design flow, an early estimation of system-level performance requires efficient simulation techniques and models to establish design requirements. In this paper we present some of the challenges associated with and efficient methods to estimate the jitter tolerance of an all-digital data recovery circuit. The key insight is that since it is the maximum slope of the phase-modulating sinusoid that causes transient bit errors, an arbitrary waveform with the same maximum slope can be used for a shorter simulation study. We also present known limitations associated with the general usage of this newly proposed method.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114064266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Adaptive digital linearization of a DRP based edge transmitter for cellular handsets 基于DRP的手机边缘发射机的自适应数字线性化
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488676
K. Waheed, S. Ba
{"title":"Adaptive digital linearization of a DRP based edge transmitter for cellular handsets","authors":"K. Waheed, S. Ba","doi":"10.1109/MWSCAS.2007.4488676","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488676","url":null,"abstract":"The digital RF processor (DRP) based EDGE small- signal polar transmitter utilizes a highly non-linear digitally controlled pre-power amplifier (DPA) for on-chip combination of the amplitude and phase modulation paths. This complex signal drives an off-chip power amplifier (PA), optimized for power added efficiency (PAE), causing further degradation in the linearity of transmission. We propose an effective adaptive predistortion scheme that takes advantage of the time division duplex (TDD) nature of the EDGE modulation and uses the on-chip receiver as a feedback path during transmission. The proposed linearization technique features automatic calibration of nominal AM-AM and AM-PM look-up tables (LUT). The temporal variations primarily caused by temperature, aging, impedance and voltage changes are compensated by an incremental predistortion function that is periodically adapted using a low complexity iterative algorithm. The proposed predistortion technique improves the EDGE TX error vector magnitude (EVM) contribution from -20 dB (or 10%) in absence of predistortion to -67 dB (0.04%) while the adjacent channel power ratio (ACPR) at 400 kHz offset improves from -46 dBc to -69 dBc.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122931545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design and implementation of an all-analog fast-fourier transform processor 全模拟快速傅立叶变换处理器的设计与实现
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488832
K. Boyle, P. Mercier, N. Sadeghi, V. Gaudet, C. Schlegel, C. Winstead, M. Kashyap
{"title":"Design and implementation of an all-analog fast-fourier transform processor","authors":"K. Boyle, P. Mercier, N. Sadeghi, V. Gaudet, C. Schlegel, C. Winstead, M. Kashyap","doi":"10.1109/MWSCAS.2007.4488832","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488832","url":null,"abstract":"The implementation of a 64-symbol analog, current-mode FFT processor is discussed. An analog FFT would be suitable for combination with an analog decoder in the making of an all-analog communication front-end for OFDM systems. Here the FFT is implemented using a butterfly diagram as the system block diagram; each node in the diagram is implemented using analog circuits. Implementation details, including consideration of the effect of approximation errors and the implementation of a test chip, are discussed.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122964648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Fully-pipelined CORDIC implementation of subspace-based speech enhancement 基于子空间的语音增强的全流水线CORDIC实现
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488546
P. Sinha, M. Swamy, P. Meher
{"title":"Fully-pipelined CORDIC implementation of subspace-based speech enhancement","authors":"P. Sinha, M. Swamy, P. Meher","doi":"10.1109/MWSCAS.2007.4488546","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488546","url":null,"abstract":"This paper presents a fully-pipelined CORDIC architecture for the simultaneous diagonalization of the covariance matrices. As an example, the problem of speech enhancement in a subspace based approach is considered, where in the covariance matrices of speech and noise are diagonalized concurrently. In order to compare the system performance of the proposed algorithm, objective measurements of speech enhancement are shown in terms of the signal to noise ratio and mean bark spectral distortion at various noise levels. In addition, the resource utilization of the proposed architecture on a Xilinx FPGA is studied.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126545360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Rapid algorithm verification for cooperative analog-digital imaging systems 协同模拟-数字成像系统快速算法验证
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488790
Teahyung Lee, Leung Kin Chiu, D.V. Anderson, R. Robucci, P. Hasler
{"title":"Rapid algorithm verification for cooperative analog-digital imaging systems","authors":"Teahyung Lee, Leung Kin Chiu, D.V. Anderson, R. Robucci, P. Hasler","doi":"10.1109/MWSCAS.2007.4488790","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488790","url":null,"abstract":"An algorithm verification methodology for cooperative analog-digital signal processing imaging system is presented, and a simulation tool for software and hardware co-verification is developed for rapid algorithm verification. Unlike traditional behavioral simulation, the behavior of the architectural structure includes the characteristics of sensor and circuit mismatch and parasitic effects so that algorithm-level simulation can predict the performance of a true physical system. A case study of gradient- based optical flow estimation algorithm is demonstrated.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126547923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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