2007 50th Midwest Symposium on Circuits and Systems最新文献_第10页

From (integrated) circuits to systems of systems on chip in five decades: How did and will (IC) test technology keep up? 五十年来从集成电路到片上系统的系统:(IC)测试技术是如何以及将如何跟上?

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488835

A. Ivanov

{"title":"From (integrated) circuits to systems of systems on chip in five decades: How did and will (IC) test technology keep up?","authors":"A. Ivanov","doi":"10.1109/MWSCAS.2007.4488835","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488835","url":null,"abstract":"The past five decades amount to mind boggling progress in IC design and manufacturing technology. In this period, we have gone from the inception of ICs to now what literally amounts to the integration of systems of systems on chip. Whereas experts debate the continued evolution of ICs according to Moore's law beyond the next decade, the advent of the complex integration of multi-physics systems is just in its infancy and is predicted to grow exponentially in the coming years. Designing and manufacturing complex ICs is of course a feat in itself. Testing and testability has often been taken for granted as a necessary (not to say evil) requirement. But who wants of an IC that cannot be duly tested, to ensure quality and reliability, especially when deployed in life-critical applications? Test technology, along with design technology has had to make enormous and rapid progress over the past half-century. Here, we highlight some of the key elements of IC test technology. We briefly mention some directions and challenges and opportunities for test technology in the near future, especially as multi-physics integrated systems of systems continue to emerge and progress on the volume production curves.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125854032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A CMOS based microfluidic detector: Design, calibration and experimental results 一种基于CMOS的微流控探测器:设计、校准和实验结果

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488568

E. Ghafar-Zadeh, M. Sawan, M. Hajj-Hassan, M. A. Miled

引用次数: 6

A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors 一种硬件/软件协作方法，用于减少特定于应用程序的指令集处理器中的内存流量

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488784

Yunsi Fei, Hai Lin, Xuan Guan

引用次数: 0

Separation of complex signals with known source distributions in time-varying channels using optimum complex block adaptive ICA 利用最优复块自适应ICA分离时变信道中已知源分布的复信号

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488606

R. Ranganathan, Thomas T. Yang, W. Mikhael

引用次数: 3

Design trade-offs for load/store buffers in embedded processing environments 在嵌入式处理环境中设计负载/存储缓冲区的权衡

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488819

Y. Kang, J. Draper

{"title":"Design trade-offs for load/store buffers in embedded processing environments","authors":"Y. Kang, J. Draper","doi":"10.1109/MWSCAS.2007.4488819","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488819","url":null,"abstract":"Memory latency is a critical issue for conventional high-speed computing platforms, and it is becoming a common problem in embedded and CMP (chip multiprocessing) systems as well. Conventional processors typically adopt caches and a load/store queue (LSQ) to address the processor-to-memory bottleneck. However, the conventional LSQ design, which has a large number of entries, is not appropriate for embedded systems due to its area and power hungry out-of- order speculation. A compact, low-power load/store buffer that also provides significant performance improvement is essential for such systems. In this paper, we propose an area-efficient wideword load/store buffer (WLSB) which supports both WideWord (256-bit) and scalar (32-bit) load/store instructions for a recently fabricated PIM (processing-in-memory) device. Given its small size, the 4 entry WLSB yields a 57.33% load hit rate on SPEC2K benchmarks. This result is 5.72% better as compared to a less area-efficient 32-entry fully associative scalar load/store buffer (SLSB). The WLSB was synthesized in IBM 90 nm technology, and the resulting implementation occupies less than a seventh of a square mm and is projected to run at 1.6 ns cycle time with 15.72 mW of dynamic power dissipation. This paper demonstrates how this very small-entry buffer can affect the load hit rate and quantifies the design trade-offs between wide small-entry and narrow large-entry buffers with respect to size, power, load hit ratio and clock speed. Although this WLSB has been specifically designed to benefit a PIM architecture, it is expected to be useful for other embedded processing platforms and CMPs due to emphasized area/power constraints.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129076283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low noise 13 GHz power efficient 16/17 prescaler with rail to rail output amplitude 低噪声13 GHz功率高效16/17预分频器，轨到轨输出幅度

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488621

E. Eschenko, M. S. Candidate, K. Entesari

{"title":"A low noise 13 GHz power efficient 16/17 prescaler with rail to rail output amplitude","authors":"E. Eschenko, M. S. Candidate, K. Entesari","doi":"10.1109/MWSCAS.2007.4488621","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488621","url":null,"abstract":"A state of the art 16/17 prescaler using current mode logic (CML) D-Flip Flops, CMOS inverters, and transmission gates for the .18mu TSMC process with a 1.8 V supply voltage is presented. The prescaler consists of a 4/5 synchronous core and a feedback loop which modulates the 4/5 core to produce a division ratio of 16/17. Instead of employing power hungry CML, the feedback circuit takes advantage of low power NOR and AND gates realized in transmission gate logic (TGL) to reduce the power consumption. To the best of our knowledge, this technique has never been used in a high frequency prescaler before. Additionally, this work will serve as a comprehensive description of the numerous considerations of prescaler design including explanation of gate-level design and transistor level optimization. Furthermore, digital circuit output is efficiently buffered with CMOS inverters for rail- to-rail operation, maximizing slew rate which minimizes phase noise. The simulated phase noise is -150 dBc/Hz @ 1 MHz and the input bandwidth is 2 GHz (11 GHz and 13 GHz). The power consumption of the entire prescaler is 18.5 mW. All of the above results were obtained from post-layout simulations. Circuit layout has been completed and sent for fabrication.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133650212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Sinusoidal RF DACs for undersampled LC bandpass ∑Δ modulabrs 欠采样LC带通∑Δ模量的正弦RF dac

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488822

N. Beilleau, C. Ouffoue, H. Aboushady

引用次数: 5

uSOL: A programming language for sensor networks 用于传感器网络的编程语言

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488690

Ramesh Bharadwaj, A. Biswas, J. James, S. Mukhopadhyay

引用次数: 0

A robust pitch detection algorithm for speech signals in a practical noisy environment 一种在实际噪声环境下对语音信号进行鲁棒基音检测的算法

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488611

C. Shahnaz, W. Zhu, M. Ahmad

引用次数: 1

A low power IC to enable optical communications in a robotic swarm 一种低功耗集成电路，可在机器人群中实现光通信

2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488702

O. Alonso, R. Casanova, A. Sanuy, A. Arbat, J. Canals, Á. Diéguez, J. Samitier

引用次数: 1