{"title":"Fully-pipelined CORDIC implementation of subspace-based speech enhancement","authors":"P. Sinha, M. Swamy, P. Meher","doi":"10.1109/MWSCAS.2007.4488546","DOIUrl":null,"url":null,"abstract":"This paper presents a fully-pipelined CORDIC architecture for the simultaneous diagonalization of the covariance matrices. As an example, the problem of speech enhancement in a subspace based approach is considered, where in the covariance matrices of speech and noise are diagonalized concurrently. In order to compare the system performance of the proposed algorithm, objective measurements of speech enhancement are shown in terms of the signal to noise ratio and mean bark spectral distortion at various noise levels. In addition, the resource utilization of the proposed architecture on a Xilinx FPGA is studied.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 50th Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2007.4488546","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a fully-pipelined CORDIC architecture for the simultaneous diagonalization of the covariance matrices. As an example, the problem of speech enhancement in a subspace based approach is considered, where in the covariance matrices of speech and noise are diagonalized concurrently. In order to compare the system performance of the proposed algorithm, objective measurements of speech enhancement are shown in terms of the signal to noise ratio and mean bark spectral distortion at various noise levels. In addition, the resource utilization of the proposed architecture on a Xilinx FPGA is studied.