2019 IEEE International Superconductive Electronics Conference (ISEC)最新文献_第6页

Noise Contribution to Switching Current Distributions in NbN Nanowires 噪声对NbN纳米线开关电流分布的影响

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990925

Ashley Qu, Di Zhu, K. Berggren

引用次数: 0

Computational Analysis of Defect Signals of All-Round Pipe Inspection using HTS-SQUID-based Guided Wave Testing 基于hts - squid的全管导波检测缺陷信号的计算分析

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990918

Y. Azuma, Y. Hatsukade

{"title":"Computational Analysis of Defect Signals of All-Round Pipe Inspection using HTS-SQUID-based Guided Wave Testing","authors":"Y. Azuma, Y. Hatsukade","doi":"10.1109/ISEC46533.2019.8990918","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990918","url":null,"abstract":"In this paper, we demonstrated all-round inspections on aluminum pipe samples with different types of defects using HTS-SQUID-based ultrasonic guided waves, and analyzed defect signals using computer simulation. In order to transceive uniformly distributed T (0, 1) mode guided waves on aluminum pipe samples, two pairs of nickel thin plates magnetized in the longitudinal direction using a solenoid coil were glued on each sample with different angle arrangement. They were used as magnetostriction-based guided wave transceivers, and a coil was wound around one pair of the nickel plates as a transmitter, while the other was used as a receiver. Artificial defects, such as a slit perpendicular to axis of the pipe and inclined slit, were made on the respective pipe samples. All-round inspection of the T (0, 1) mode guided waves around circumferences of the pipes were carried out by rotating the pipe for 360° with step of 45°. Signals of reflected wave from the artificial slits were well detected. We simulated distribution of the guided waves propagating on the pipes with the slits using an ultrasonic simulator for two-dimensional models. The guided wave signal distributions including the defect signals obtained by experiments and simulations agreed well.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126396083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of self-induced flux in parallel arrays of Josephson junctions 约瑟夫逊结平行阵列中自感应磁通的影响

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990895

D. Crété, Y. Lemaître, B. Marcilhac, J. Trastoy, C. Ulysse

引用次数: 1

Reconfigurable Logic Cell for Superconducting Magnetic Field Programmable Gate Array 超导磁场可编程门阵列的可重构逻辑单元

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990919

N. Katam, Haolin Cong, M. Pedram

{"title":"Reconfigurable Logic Cell for Superconducting Magnetic Field Programmable Gate Array","authors":"N. Katam, Haolin Cong, M. Pedram","doi":"10.1109/ISEC46533.2019.8990919","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990919","url":null,"abstract":"Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121711721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Timing Verification for Rapid Single-Flux-Quantum (RSFQ) Logic: New Paradigm and Models 快速单通量量子(RSFQ)逻辑的时序验证:新范式和新模型

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990904

Fangzhou Wang, S. Gupta

{"title":"Timing Verification for Rapid Single-Flux-Quantum (RSFQ) Logic: New Paradigm and Models","authors":"Fangzhou Wang, S. Gupta","doi":"10.1109/ISEC46533.2019.8990904","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990904","url":null,"abstract":"RSFQ is an attractive technology due to its low energy and high speed. However, it is imperative to certify speed for each design (via timing verification) and each fabricated chip (via delay testing). In this paper, we describe completely new phenomena in RSFQ circuits that arise due to their unique characteristics and require the development of new concepts, methods, and tools for timing verification and delay testing. We show that single-pattern timing verification and delay testing is possible in RSFQ technology. We also show that due to the gate-level pipelined nature of RSFQ circuits, imposing a guard-band to resolve the setup time issue will reduce the performance dramatically and lose some of the speed benefits of RSFQ. More importantly, inserting scan logic for every pipelined gate in RSFQ will cause astronomical area overheads. Therefore, the increased clock-to-Q delay (i.e., timing bleed) must be allowed, and delay faults in fabricated chip must be tested for multi-cycle paths. Further, the polarity of the logic gate is an important determinant for selecting target multi-cycle path. Also, we have observed a completely new delay failure behavior in RSFQ. If the clock period is insufficient compared to circuit delays, in addition to a missing pulse at output in one clock cycle, an additional pulse can be generated in the next cycle. This provides additional opportunities to detect timing problems for timing verification and delay testing. In addition to describing above major differences from CMOS and their implications, we outline a completely new paradigm for Automatic Test Pattern Generation (ATPG) for timing verification and delay testing of RSFQ circuits.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129140324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Reducing the Maximum Length of Connections in Single Flux Quantum Circuits During Routing 减少单通量量子电路在路由过程中的最大连接长度

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990897

Ting-Ru Lin, M. Pedram

引用次数: 0

qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit 一个32位块倾斜RSFQ算术逻辑单元的逻辑设计

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990921

Souvik Kundu, G. Datta, P. Beerel, M. Pedram

{"title":"qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit","authors":"Souvik Kundu, G. Datta, P. Beerel, M. Pedram","doi":"10.1109/ISEC46533.2019.8990921","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990921","url":null,"abstract":"Single flux quantum (SFQ) circuits are an attractive beyond-CMOS technology because they promise two orders of magnitude lower power at clock frequencies exceeding 25 GHz. However, every SFQ gate is clocked creating very deep gate-level pipelines that are difficult to keep full, particularly for sequences that include data-dependent operations. This paper proposes to increase the throughput of SFQ pipelines by redesigning the datapath to accept and operate on least-significant bits (LSBs) clock cycles earlier than more significant bits. This skewed datapath approach reduces the latency of the LSB side which can be feedback earlier for use in subsequent data-dependent operations increasing their throughput. In particular, we propose to group the bits into 4-bit blocks that are operated on concurrently and create block-skewed datapath units for 32-bit operation. This skewed approach allows a subsequent data-dependent operation to start evaluating as soon as the first 4-bit block completes. Using this general approach, we develop a block-skewed MIPS-compatible 32-bit ALU. Our gate-level Verilog design improves the throughput of 32-bit data dependent operations by 2x and 1.5x compared to previously proposed 4-bit bit-slice and 32-bit Ladner-Fischer ALUs respectively. We have quantified the benefit of this design on instructions per cycle (IPC) for various RISC-V benchmarks assuming a range of non-ALU operation latencies from one to ten cycles. Averaging across benchmarks, our experimental results show that compared to the 32-bit Ladner-Fischer our proposed architecture provides a range of IPC improvements between 1.37x assuming one-cycle non-ALU latency to 1.2x assuming ten-cycle non-ALU latency. Moreover, our average IPC improvements compared to a 32-bit ALU based on the 4-bit bit-slice range from 2.93x to 4x.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125443412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Improved Transmission Line Parameter Calculation through TCAD Process Modeling for Superconductor Integrated Circuit Interconnects 利用TCAD过程建模改进超导集成电路互连传输线参数计算

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990927

H. F. Herbst, P. Le Roux, Kyle Jackman, C. Fourie

引用次数: 9

Estimation of Focused Helium Ion Beam Josephson Junction Width 聚焦氦离子束约瑟夫森结宽度的估计

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990939

Yan-Ting Wang, E. Cho, Hao Li, S. Cybart

引用次数: 3

Development of Programmable Integrated Quantum Voltage Noise Source 可编程集成量子电压噪声源的研制

2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990935

C. Urano, T. Irimatsugawa, Takahiro Yamada

引用次数: 1