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2019 IEEE International Superconductive Electronics Conference (ISEC)最新文献

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Bias Field Gradient Effects of Large Superconducting Quantul Inteference Device (SQUID) Arrays (SQAs) 大型超导量子干涉器件(SQUID)阵列的偏置场梯度效应
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990951
S. Berggren, B. Taylor, M. O'Brien, A. D. de Escobar, M. D. de Andrade
{"title":"Bias Field Gradient Effects of Large Superconducting Quantul Inteference Device (SQUID) Arrays (SQAs)","authors":"S. Berggren, B. Taylor, M. O'Brien, A. D. de Escobar, M. D. de Andrade","doi":"10.1109/ISEC46533.2019.8990951","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990951","url":null,"abstract":"In this investigation we explore the effects of nonuniform magnetic bias fields on the voltage-flux curve of large two-dimensional arrays of superconducting quantum interference devices (SQUIDs). The SQUID arrays (SQAs) contain 1020 SQUIDs modeled with parallel coupling in the x-direction and series coupling in the y-direction. Each array is composed of individual SQUID elements having non-uniform size loop areas, resulting in a non-uniform inductance parameter $beta_{L}$, and a single “anti-peak” feature at zero magnetic field in the voltage-flux transfer function. We examine the changed induced in the profile of the transfer function by gradients in the magnetic field in both the x- and y-directions. The height, slope, and symmetry of the anti-peak feature is compared with that from the same SQA exposed to a uniform field.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127389591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Nb5N6 Buffered Superconducting NbN Nanowire Single-Photon Detector on Si Substrate 硅衬底Nb5N6缓冲超导NbN纳米线单光子探测器
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990948
Tao Xu, Jian Chen, Peiheng Wu, X. Jia, Shi Chen, Xiaoying Zhou, Jin Jin, X. Tu, La-bao Zhang, Qingyuan Zhao, L. Kang
{"title":"Nb5N6 Buffered Superconducting NbN Nanowire Single-Photon Detector on Si Substrate","authors":"Tao Xu, Jian Chen, Peiheng Wu, X. Jia, Shi Chen, Xiaoying Zhou, Jin Jin, X. Tu, La-bao Zhang, Qingyuan Zhao, L. Kang","doi":"10.1109/ISEC46533.2019.8990948","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990948","url":null,"abstract":"Superconducting nanowire single photon detectors (SNSPDs) based on Si substrates have demonstrated excellent performance, such as high efficiency, low dark count rate, short reset time and low timing jitter. But due to the lattice mismatch between NbN and Si substrate, the performance of film is limited. To this end, Nb5N6 layer is fabricated as the buffer layer between the NbN film and Si substrate, and that will reduce the mismatch and optimize superconducting properties of NbN films. The 6nm-thick film with a 65 nm-thick buffer layer shows the zero resistance critical temperature (Tc0) of 13.27 K, which is 5 K higher than that without buffer. Based on the NbN film on the buffered substrate, we fabricated SNSPD devices demonstrate critical current $(mathrm{I}_{mathrm{C}})$ of $65 mu mathrm{A}$ which is $5 sim 6$ times higher to the detectors without buffer. Besides, the experiment results prove that the buffer layer reduces the kinetic inductance, which fasten the recovery of nanowire.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126841405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulating the Fabrication of Nb/Al-O/Nb Josephson Junction for Superconductive Electronics Application 超导电子应用中Nb/Al-O/Nb Josephson结的模拟制备
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990907
N. Pokhrel, T. Weingartner, Robert J. Burwell, E. Patrick, M. Law
{"title":"Simulating the Fabrication of Nb/Al-O/Nb Josephson Junction for Superconductive Electronics Application","authors":"N. Pokhrel, T. Weingartner, Robert J. Burwell, E. Patrick, M. Law","doi":"10.1109/ISEC46533.2019.8990907","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990907","url":null,"abstract":"Josephson junction devices enable computation of binary data by switching between superconductive and resistive states. The switching is triggered by a current flowing through the junction below or above the critical limit $(I_{c})$, which is sensitive to the physical features of the junction. Modeling the variation in the physical properties of these tunnel junctions due to processing conditions is crucial to understanding the variation in $I_{c}$ across the chip and simulating the electrical characteristics of the device. The aim of this research is to model the steps involved in the fabrication of Nb/Al-O/Nb Josephson Junction for large scale integrated superconductive circuits, which consists of mainly: (i) sputter deposition of Al on top of the Nb base electrode (ii) oxidation of the Al layer to form Al-O tunnel barrier (~1nm] and (iii) anodization of the junction. Developing a process TCAD tool by implementing the fabrication steps from the base layer will ultimately complement device simulation and offer useful insights for optimization.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130898360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Pulse-Driven High- TC Josephson Junctions for Quantum Voltage Devices 用于量子电压器件的脉冲驱动高TC约瑟夫森结
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990942
A. Weis, N. Flowers-Jacobs, E. Cho, H. Li, J. LeFebvre, S. Cybart, S. Berkowitz, H. Rogalla, S. Benz
{"title":"Pulse-Driven High- TC Josephson Junctions for Quantum Voltage Devices","authors":"A. Weis, N. Flowers-Jacobs, E. Cho, H. Li, J. LeFebvre, S. Cybart, S. Berkowitz, H. Rogalla, S. Benz","doi":"10.1109/ISEC46533.2019.8990942","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990942","url":null,"abstract":"Josephson junction arrays are the basis for quantum-accurate dc and ac voltage standards, including artificial voltage-noise references used in noise thermometry. I will describe our recent progress towards voltage synthesis using high-transition-temperature YBCO junctions.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133271207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of an SFQ Full Adder as a Single-Stage Gate 作为单级门的SFQ全加法器设计
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990964
Haolin Cong, N. Katam, M. Pedram
{"title":"Design of an SFQ Full Adder as a Single-Stage Gate","authors":"Haolin Cong, N. Katam, M. Pedram","doi":"10.1109/ISEC46533.2019.8990964","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990964","url":null,"abstract":"This paper presents the design of a one-bit full adder with sum and carry outputs as two single-stage gates, which could save the JJ count and the area compared with the conventional design of a full-adder. The schematics of both the Sum and Carry cells are shown in this paper along with their input and output waveforms of JSIM simulations in the time domain. The circuit cost is compared between the conventional full adder and the new single-stage adder design in terms of the area and the time. Integer dividers of several sizes are synthesized with conventional full-adder and the proposed single-stage adder to illustrate the advantages of the new design.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122154007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Portable Solid Nitrogen Cooling System for High Transition Temperature Superconductive Electronics 用于高温超导电子器件的便携式固体氮冷却系统
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990924
Ji Wang, E. Cho, Hao Li, J. LeFebvre, Kevin Pratt, S. Cybart
{"title":"Portable Solid Nitrogen Cooling System for High Transition Temperature Superconductive Electronics","authors":"Ji Wang, E. Cho, Hao Li, J. LeFebvre, Kevin Pratt, S. Cybart","doi":"10.1109/ISEC46533.2019.8990924","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990924","url":null,"abstract":"In this work we present a miniature solid nitrogen cooling system designed for 45 K operation of $(mathrm{high}-T_{mathrm{C}})$ superconductor Josephson devices. The system utilizes a small 100mL fiberglass Dewar and external pump to solidify nitrogen in thermal contact with a circuit board insert. Cooling tests reveal that the system holds at its base temperature of 45 K for over 12 hours. This can provide a low power, low weight system for ultra-portable superconductive electronics and other cryogenic sensors.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131812813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Logic Design of an 8-bit RSFQ Microprocessor 8位RSFQ微处理器的逻辑设计
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990959
Jia-Hong Yang, Guangming Tang, Pei-Yao Qu, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun
{"title":"Logic Design of an 8-bit RSFQ Microprocessor","authors":"Jia-Hong Yang, Guangming Tang, Pei-Yao Qu, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun","doi":"10.1109/ISEC46533.2019.8990959","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990959","url":null,"abstract":"An 8-bit bit-parallel RSFQ microprocessor, named HUTU, is proposed. It can execute 28 different instructions. Each instruction consists of eight bits. Harvard-type architecture is adopted for parallel processing between the control unit and the datapath. The control unit uses an asynchronous timing method to avoid pipeline flushing and to reduce the area. Concurrent-flow clocking is adopted in the datapath for high performance. The simulation result shows that the elements of HUTU run correctly.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"5 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124529882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits 超导单通量量子电路的统计静态时序分析工具
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-07-01 DOI: 10.1109/ISEC46533.2019.8990954
Bo Zhang, Fangzhou Wang, S. Gupta, M. Pedram
{"title":"A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits","authors":"Bo Zhang, Fangzhou Wang, S. Gupta, M. Pedram","doi":"10.1109/ISEC46533.2019.8990954","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990954","url":null,"abstract":"As a beyond-CMOS technology, superconducting single-flux-quantum (SFQ) technology promises fast processing speed and excellent energy efficiency. With the increasing complexity of SFQ circuits, the accurate and fast estimation of the workable clock period under process variation becomes more urgent. However, the estimation of the minimum workable clock period is difficult due to the spatial correlation of physical parameters and the non-normal distribution of timing parameters (propagation delay, setup time, and hold time). Therefore, a good statistical timing analysis (SSTA) tool for SFQ circuits is necessary. This paper presents a bootstrap-based statistical static timing analysis tool called qSSTA. qSSTA can reasonably estimate a minimum workable clock period by executing a large amount of bootstrap iterations from the discrete sampling spaces of all gates under a certain correlation specification. By applying path pruning methods, qSSTA skips the calculations on unimportant paths and hence reduce run time and memory. Experimental results show that the size of important paths could be small. Among 19114 paths of the 16-bit integer divider, only 73 paths are important to estimate minimum workable clock period. We only need 84.21 seconds to run 10,000 iterations.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121764570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Direct-Write Ion Beam Irradiated Josephson Junctions 直写离子束辐照约瑟夫森结
2019 IEEE International Superconductive Electronics Conference (ISEC) Pub Date : 2019-06-25 DOI: 10.1109/ISEC46533.2019.8990934
E. Cho, Hao Li, S. Cybart
{"title":"Direct-Write Ion Beam Irradiated Josephson Junctions","authors":"E. Cho, Hao Li, S. Cybart","doi":"10.1109/ISEC46533.2019.8990934","DOIUrl":"https://doi.org/10.1109/ISEC46533.2019.8990934","url":null,"abstract":"We highlight the reproducibility and level of control over the electrical properties of YBa2Cu3O7 Josephson junctions fabricated with irradiation from a focused helium ion beam. Specifically we show the results of electrical transport properties for several junctions fabricated using a large range of irradiation doses. At the lower end of this range, junctions exhibit superconductor-normal metal-superconductor (SNS) Josephson junction properties. However, as dose increases there is a transition to electrical characteristics consistent with superconductor-insulator-superconductor (SIS) junctions. To investigate the uniformity of large numbers of helium ion Josephson junctions we fabricate arrays of both SNS and SIS Josephson junctions containing 20 connected in series. Electrical transport properties for these arrays reveal very uniform junctions with no appreciable spread in critical current or resistance.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129380267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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