Jia-Hong Yang, Guangming Tang, Pei-Yao Qu, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun
{"title":"8位RSFQ微处理器的逻辑设计","authors":"Jia-Hong Yang, Guangming Tang, Pei-Yao Qu, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun","doi":"10.1109/ISEC46533.2019.8990959","DOIUrl":null,"url":null,"abstract":"An 8-bit bit-parallel RSFQ microprocessor, named HUTU, is proposed. It can execute 28 different instructions. Each instruction consists of eight bits. Harvard-type architecture is adopted for parallel processing between the control unit and the datapath. The control unit uses an asynchronous timing method to avoid pipeline flushing and to reduce the area. Concurrent-flow clocking is adopted in the datapath for high performance. The simulation result shows that the elements of HUTU run correctly.","PeriodicalId":250606,"journal":{"name":"2019 IEEE International Superconductive Electronics Conference (ISEC)","volume":"5 17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Logic Design of an 8-bit RSFQ Microprocessor\",\"authors\":\"Jia-Hong Yang, Guangming Tang, Pei-Yao Qu, Xiao-Chun Ye, D. Fan, Zhimin Zhang, Ning-Hui Sun\",\"doi\":\"10.1109/ISEC46533.2019.8990959\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 8-bit bit-parallel RSFQ microprocessor, named HUTU, is proposed. It can execute 28 different instructions. Each instruction consists of eight bits. Harvard-type architecture is adopted for parallel processing between the control unit and the datapath. The control unit uses an asynchronous timing method to avoid pipeline flushing and to reduce the area. Concurrent-flow clocking is adopted in the datapath for high performance. The simulation result shows that the elements of HUTU run correctly.\",\"PeriodicalId\":250606,\"journal\":{\"name\":\"2019 IEEE International Superconductive Electronics Conference (ISEC)\",\"volume\":\"5 17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Superconductive Electronics Conference (ISEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISEC46533.2019.8990959\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Superconductive Electronics Conference (ISEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISEC46533.2019.8990959","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 8-bit bit-parallel RSFQ microprocessor, named HUTU, is proposed. It can execute 28 different instructions. Each instruction consists of eight bits. Harvard-type architecture is adopted for parallel processing between the control unit and the datapath. The control unit uses an asynchronous timing method to avoid pipeline flushing and to reduce the area. Concurrent-flow clocking is adopted in the datapath for high performance. The simulation result shows that the elements of HUTU run correctly.