Timing Verification for Rapid Single-Flux-Quantum (RSFQ) Logic: New Paradigm and Models

Abstract

RSFQ is an attractive technology due to its low energy and high speed. However, it is imperative to certify speed for each design (via timing verification) and each fabricated chip (via delay testing). In this paper, we describe completely new phenomena in RSFQ circuits that arise due to their unique characteristics and require the development of new concepts, methods, and tools for timing verification and delay testing. We show that single-pattern timing verification and delay testing is possible in RSFQ technology. We also show that due to the gate-level pipelined nature of RSFQ circuits, imposing a guard-band to resolve the setup time issue will reduce the performance dramatically and lose some of the speed benefits of RSFQ. More importantly, inserting scan logic for every pipelined gate in RSFQ will cause astronomical area overheads. Therefore, the increased clock-to-Q delay (i.e., timing bleed) must be allowed, and delay faults in fabricated chip must be tested for multi-cycle paths. Further, the polarity of the logic gate is an important determinant for selecting target multi-cycle path. Also, we have observed a completely new delay failure behavior in RSFQ. If the clock period is insufficient compared to circuit delays, in addition to a missing pulse at output in one clock cycle, an additional pulse can be generated in the next cycle. This provides additional opportunities to detect timing problems for timing verification and delay testing. In addition to describing above major differences from CMOS and their implications, we outline a completely new paradigm for Automatic Test Pattern Generation (ATPG) for timing verification and delay testing of RSFQ circuits.