International Conferencre on Simulation of Semiconductor Processes and Devices最新文献

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On the large-signal CMOS modeling and parameter extraction for RF applications 射频应用中的大信号CMOS建模与参数提取
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034518
M. Je, I. Kwon, Jeonghu Han, Hyungcheol Shin, Kwyro Lee
{"title":"On the large-signal CMOS modeling and parameter extraction for RF applications","authors":"M. Je, I. Kwon, Jeonghu Han, Hyungcheol Shin, Kwyro Lee","doi":"10.1109/SISPAD.2002.1034518","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034518","url":null,"abstract":"A small-signal equivalent circuit of an RF MOSFET not only fully compatible with 4 terminal large-signal quasi-static I-V and Q-V models but suitable for 3 terminal two-port s-parameter measurement, is proposed along with very simple and accurate parameter extraction method. This model includes the intrinsic and extrinsic elements important for AC simulation at RF. The validity and accuracy of our approach is verified from 0.18 /spl mu/m RF NMOS results.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129232622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Simulation of DGSOI MOSFETs with a Schrodinger-Poisson based mobility model 基于薛定谔-泊松迁移率模型的DGSOI mosfet模拟
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034507
A. Schenk, A. Wettstein
{"title":"Simulation of DGSOI MOSFETs with a Schrodinger-Poisson based mobility model","authors":"A. Schenk, A. Wettstein","doi":"10.1109/SISPAD.2002.1034507","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034507","url":null,"abstract":"Ultra-thin DGSOI transistors are considered as one of the most promising devices for future VLSI. Besides expected improvements in the sub-threshold behavior, a theoretical enhancement of the channel mobility was found by some authors. Here, we apply a quantum-mechanical mobility model, based on an integrated Schrodinger/Poisson solver, to double-gate SOI MOSFETs with a range of silicon slab thickness t/sub Si/ and buried-oxide thickness t/sub box/. The main finding is that the theoretical enhancement of effective mobility and on-current at t/sub Si/ /spl ap/10 nm is bound to comparable thicknesses of buried and front oxides. If t/sub box/ /spl ap/100/spl times/t/sub ox/, as e.g. in the case of SIMOX wafers, the volume-inversion related increase of the mobility completely vanishes.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115830122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
2D simulation of a buried-heterostructure tunable twin-guide DFB laser diode 埋藏异质结构可调谐双波导DFB激光二极管的二维仿真
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034515
L. Schneider, T. Witzig, W. Streiff, W. Pfeiffer, T. Bregy, T. Schmidt, W. Fichtner
{"title":"2D simulation of a buried-heterostructure tunable twin-guide DFB laser diode","authors":"L. Schneider, T. Witzig, W. Streiff, W. Pfeiffer, T. Bregy, T. Schmidt, W. Fichtner","doi":"10.1109/SISPAD.2002.1034515","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034515","url":null,"abstract":"A 2D simulation of an InGaAsP-InP buried-heterostructure tunable twin-guide (TTG) DFB laser diode is performed. The device structure is optimized with respect to maximal tuning range and output power. To minimize the current leakage around the active region, a p-n-p-n current blocking region is also modeled and its effect on the laser characteristics is discussed. Good agreement between simulation and measurements is obtained.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124748094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A strategy for enabling predictive TCAD in development of sub-100nm CMOS technologies 在亚100nm CMOS技术开发中实现预测性TCAD的策略
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034510
C. Machala, S. Chakravarthi, D. Li, S. Yang, C. Bowen
{"title":"A strategy for enabling predictive TCAD in development of sub-100nm CMOS technologies","authors":"C. Machala, S. Chakravarthi, D. Li, S. Yang, C. Bowen","doi":"10.1109/SISPAD.2002.1034510","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034510","url":null,"abstract":"CMOS technology development is an expensive undertaking. Predictive TCAD can be a key tool in reducing the time and cost of CMOS development by acting as a virtual wafer fah where experimental lots are first simulated and the results analyzed before the first process step is ever run. In this way errors may be uncovered, poor splits eliminated and inadequate experimental designs improved. Each lot yields more information through better design and less waste. However, in order to achieve these improvements TCAD simulators must be quickly calibrated with new models that simulate the new physics for sub-100nm technology nodes. Because of the rapid pace of CMOS development, the available commercial simulators do not usually contain all the models needed in order to be predictive. This paper describes our efforts in upgrading the commercially available simulators TSUPREM4 and Dessis for the purpose of aiding in the development of sub-100nm high performance and low stand-by power CMOS technologies.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114507908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis of injection current with electron temperature for high-K gate stacks 高钾栅极堆注入电流随电子温度的变化分析
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034563
Y. Ohkura, H. Takashino, S. Wakahara, K. Nishi
{"title":"Analysis of injection current with electron temperature for high-K gate stacks","authors":"Y. Ohkura, H. Takashino, S. Wakahara, K. Nishi","doi":"10.1109/SISPAD.2002.1034563","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034563","url":null,"abstract":"Though, high dielectric constant material is a possible near future candidate to suppress gate current densities of MOSFETs, the barrier height generally decreases with increasing dielectric constant. In this paper, the injection current through gate stacks has been calculated while taking into account the electron temperature using the W.K.B. method to understand the impact of the injection current from the drain edge.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121378789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The physical phenomena responsible for excess noise in short-channel MOS devices
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034520
R. Navid, R. Dutton
{"title":"The physical phenomena responsible for excess noise in short-channel MOS devices","authors":"R. Navid, R. Dutton","doi":"10.1109/SISPAD.2002.1034520","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034520","url":null,"abstract":"The physical phenomena responsible for the excess noise in short-channel MOS devices are explained based on the non-equilibrium noise theory. Comparing the MOS excess noise with the well known excess noise in a mesoscopic conductor, it is suggested that the physical origins of both are the same. Using this theory, it is proposed that the noise sources used in the impedance field method (IFM) should contain not only the usual thermal noise component, but also a partially suppressed shot noise term which accounts for the limited number of inelastic scattering events in the channel. The theoretical predictions of a simplified model based on this theory are presented and compared with the measurement results. It is shown both theoretically and experimentally that the non-equilibrium noise component is smaller when a larger gate to source voltage is applied. The accurate calculation of the suppression factor, which is in general a function of device terminal voltages, remains a challenge.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"35 1 pt A 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128606572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Simulation of substrate currents 衬底电流模拟
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034521
W. Schoenmaker, P. Meuris, W. Magnus, B. Maleszka
{"title":"Simulation of substrate currents","authors":"W. Schoenmaker, P. Meuris, W. Magnus, B. Maleszka","doi":"10.1109/SISPAD.2002.1034521","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034521","url":null,"abstract":"Recently a new approach was presented to determine the high-frequency response of on-chip passive components and interconnects. The method solves the electric scalar and magnetic vector potentials in a prescribed gauge. The latter one is included by introducing an additional independent scalar field, whose field equation needs to be solved. This additional field is a mathematical aid that allows for the construction of a gauge-conditioned, regular matrix representation of the curl-curl operator acting on edge elements. This paper reports on the convergence properties of the new method and shows the first results of this new calculation scheme for VLSI-based structures at high frequencies. The high-frequent behavior of the substrate current, the skin effect and current crowding is evaluated.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127120831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET 非对称高压mosfet直流和交流精确仿真的偏置相关漂移电阻建模
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034552
N. Hefyene, E. Vestiel, Benoit Bakeroot, C. Anghel, S. Frere, Adrian M. Ionescu, Renaud Gillon
{"title":"Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET","authors":"N. Hefyene, E. Vestiel, Benoit Bakeroot, C. Anghel, S. Frere, Adrian M. Ionescu, Renaud Gillon","doi":"10.1109/SISPAD.2002.1034552","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034552","url":null,"abstract":"A detailed investigation of the drift resistance evolution with the gate and drain biases in Lateral DMOS architectures is reported. The extractions are performed using the concept of intrinsic drain voltage, V/sub K/, applied to both simulated and measured data. Some new special test structures (MESDRIFT) have been designed and fabricated in order to investigate the DMOS bias-dependent drift resistance and experimentally confirm 2D numerical simulations. Some of the physical origins, associated with drift resistance dependence on gate and drain bias, are discussed. A simple yet efficient DMOS macro-modeling strategy is reported. It consists of combining a low-voltage BSIM model module with a bias-dependent series resistance described by a quasi-empirical mathematical expression. All LDMOS operation regimes (including quasi-saturation) are captured by the proposed expression and data measured on MESDRIFT is used to calibrate the BSIM and drift parameters. The methodology does not dependent on the drift architecture and can be applied to any similar asymmetric HV MOS devices.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123866491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Simulation of direct source-to-drain tunnelling using the density gradient formalism: Non-Equilibrium Greens Function calibration 使用密度梯度形式的直接源-漏隧道模拟:非平衡格林函数校准
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034569
J. Watling, A. Brown, A. Asenov, A. Svizhenko, M. Anantram
{"title":"Simulation of direct source-to-drain tunnelling using the density gradient formalism: Non-Equilibrium Greens Function calibration","authors":"J. Watling, A. Brown, A. Asenov, A. Svizhenko, M. Anantram","doi":"10.1109/SISPAD.2002.1034569","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034569","url":null,"abstract":"Quantum mechanical confinement effects, gate, hand-to-hand and source-to-drain tunnelling will dramatically affect the characteristics of future generation nanometre scaled devices. It has been demonstrated already that first-order quantum corrections, which satisfactorily describe quantum confinement effects, can be introduced into efficient TCAD orientated drift-diffusion simulators using the density gradient approach. In this paper we refer to Non-Equilibrium Green's Function simulations in order to calibrate the density gradient formalism in respect of both confinement and source-to-drain tunnelling using different effective masses in directions normal and parallel to the conducting channel. We demonstrate that the density gradient formalism can describe accurately the current characteristics in sub 20 nm double gate MOSFETs.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115164463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Technology modeling for emerging SOI devices 新兴SOI设备的技术建模
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034558
M. Ieong, P. Oldiges
{"title":"Technology modeling for emerging SOI devices","authors":"M. Ieong, P. Oldiges","doi":"10.1109/SISPAD.2002.1034558","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034558","url":null,"abstract":"New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. We discuss key modeling tools and methodologies used to support research, development, and manufacturing of emerging SOI device technology. Although commercial TCAD tools are available, new physical models, parameters, and algorithms are needed to study these novel device structures.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"1522 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116502150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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