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International Conferencre on Simulation of Semiconductor Processes and Devices最新文献

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A strategy to enforce the discrete minimax principle on finite element meshes 一种在有限元网格上执行离散极大极小原则的策略
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034547
T. Binder, H. Ceric, A. Hossinger, S. Selberherr
{"title":"A strategy to enforce the discrete minimax principle on finite element meshes","authors":"T. Binder, H. Ceric, A. Hossinger, S. Selberherr","doi":"10.1109/SISPAD.2002.1034547","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034547","url":null,"abstract":"Low quality meshes in three-dimensional finite element diffusion simulations often violate the discrete Minimax principle. An indication of this shortcoming is the occurrence of negative concentrations. We present an a posteriori refinement algorithm to enforce the discrete Minimax principle by locally refining the mesh based on the last time-step. Two examples of diffusion simulations where negative concentrations could effectively be avoided by applying our refinement algorithm are presented. A final example is given to demonstrate the locality of the algorithm.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116587241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of ultra shallow junctions and hybrid source/drain profiles annealed by soak and spike RTA 浸泡和尖峰RTA退火的超浅结和混合源/漏剖面的建模
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034539
C.C. Wang, C.S. Chang, P. Griffin, C. H. Diaz
{"title":"Modeling of ultra shallow junctions and hybrid source/drain profiles annealed by soak and spike RTA","authors":"C.C. Wang, C.S. Chang, P. Griffin, C. H. Diaz","doi":"10.1109/SISPAD.2002.1034539","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034539","url":null,"abstract":"We discuss the 1D/2D modeling of arsenic profiles under soak and spike anneal conditions at both shallow extension and high concentration source/drain areas. This work also addresses the calibration of the phosphorus profile in a hybrid (arsenic + phosphorus) source/drain with various anneal temperatures. It is shown that the \"+1\" or modified \"+n\" model is not necessary for shallow arsenic profile modeling under spike anneal conditions. Finally, it is also shown that modeling of the hybrid source/drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity, initial value of point defects concentration at equilibrium state, and neglect of implant induced damage.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cross validation of quantum simulations and optical measurements in single electron memories with silicon nano-crystallites 硅纳米微晶单电子存储器中量子模拟与光学测量的交叉验证
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034546
A. Poncet, C. Busseret, A. Souifi
{"title":"Cross validation of quantum simulations and optical measurements in single electron memories with silicon nano-crystallites","authors":"A. Poncet, C. Busseret, A. Souifi","doi":"10.1109/SISPAD.2002.1034546","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034546","url":null,"abstract":"Quantum simulations of single electron memories (SEM) have been performed on single nano-crystals, axisymmetrical and far enough from their neighbors to allow Poisson and Schrodinger equations to be solved in polar coordinates. The variations of the transition energies with respect to the shape of the dots is discussed, arriving to the conclusion that the major dependency is with respect to the volume of the dots, while the tunneling current depends more on their flatness. For the first time, numerical simulation results are cross checked with photoluminescence and absorption measurements in silicon quantum dots.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130028211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simulations of ultrathin, ultrashort double-gated MOSFETs with the density gradient transport model 用密度梯度输运模型模拟超薄、超短双门mosfet
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034570
E. Lyumkis, R. Mickevicius, O. Penzin, B. Polsky, K. El Sayed, A. Wettstein, W. Fichtner
{"title":"Simulations of ultrathin, ultrashort double-gated MOSFETs with the density gradient transport model","authors":"E. Lyumkis, R. Mickevicius, O. Penzin, B. Polsky, K. El Sayed, A. Wettstein, W. Fichtner","doi":"10.1109/SISPAD.2002.1034570","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034570","url":null,"abstract":"We report the results of numerical simulation of nanoscale SOI structures under highly non-equilibrium conditions with the Density Gradient model. The simulations have been carried out with the general purpose device simulator DESSIS. We show that 2D quantum mechanical effects are important for the structures under investigation. We demonstrate that our implementation of the DG model is robust and enables efficient simulation far from equilibrium, for both the drift-diffusion and hydrodynamic transport model.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114671292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Circuit-simulation model of gate-drain-capacitance changes in small-size MOSFETs due to high channel-field gradients 高通道场梯度下小尺寸mosfet栅极-漏极-电容变化的电路仿真模型
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034514
D. Navarro, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Kawano, H. Ueno, M. Miura-Mattausch, H. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, N. Nakayama
{"title":"Circuit-simulation model of gate-drain-capacitance changes in small-size MOSFETs due to high channel-field gradients","authors":"D. Navarro, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Kawano, H. Ueno, M. Miura-Mattausch, H. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, N. Nakayama","doi":"10.1109/SISPAD.2002.1034514","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034514","url":null,"abstract":"The field gradient along the MOSFET channel is included in the modeling of the gate-drain capacitance (C/sub gd/) by an induced capacitance approach. The new approach has been successfully implemented in surface-potential based model HiSIM (Hiroshima-university STARC IGFET Model) and is capable of reproducing measured effects, which are particularly significant for pocket-implant technology, accurately.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122979187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the optimal shape and location of silicided source and drain contacts 硅化源漏触点的最佳形状和位置
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034511
P. Oldiges, C. Murthy, Xinlin Wang, S. Fung, R. Purtell
{"title":"On the optimal shape and location of silicided source and drain contacts","authors":"P. Oldiges, C. Murthy, Xinlin Wang, S. Fung, R. Purtell","doi":"10.1109/SISPAD.2002.1034511","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034511","url":null,"abstract":"A detailed simulation and analysis of the source/drain resistance is performed. It is shown that the placement and depth of silicide regions can have a strong influence on the total source/drain resistance. Simulations further show that moving the silicided regions closer to the channel of a device will not necessarily decrease source/drain resistance, and may actually cause the resistance to increase. Lumped contact resistance, distributed resistance, Schottky contact models, and a new local distributed resistance model are compared.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125653712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design GIDL仿真与优化用于0.13 /spl mu/m/1.5 V低功耗CMOS晶体管设计
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034512
Song Zhao, Shaoping Tang, M. Nandakumar, D. Scott, S. Sridhar, A. Chatterjee, Youngmin Kim, Shyh-Horng Yang, Shi-Charng Ai, S. Ashburn
{"title":"GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design","authors":"Song Zhao, Shaoping Tang, M. Nandakumar, D. Scott, S. Sridhar, A. Chatterjee, Youngmin Kim, Shyh-Horng Yang, Shi-Charng Ai, S. Ashburn","doi":"10.1109/SISPAD.2002.1034512","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034512","url":null,"abstract":"In this work, we calibrate a BTBT model based on measured GIDL data, and incorporate the model into our process/device simulations to directly correlate process with device performance and leakage. For the first time, we quantitatively explore an overall picture of tradeoffs between device leakage and performance as functions of process conditions. The explored design space has been used in process optimization for our 0.13 /spl mu/m/1.5 V low power (LP) CMOS transistors. We demonstrate that such predictive TCAD simulations to determine and optimize process conditions can effectively reduce development time and cost. We describe GIDL mechanisms in our 0.13 /spl mu/m/1.5 V LP transistors, and explain, via simulations, that the measured GIDL current manifests different IN behaviors depending on whether the dominant BTBT location is at the gate oxide/Si interface or below in the Si bulk.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127349494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Perspectives in microscopic carrier transport 微观载体输运的展望
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034503
T. Ando
{"title":"Perspectives in microscopic carrier transport","authors":"T. Ando","doi":"10.1109/SISPAD.2002.1034503","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034503","url":null,"abstract":"A brief review is given of recent investigation of transport properties of nanostructures from semiconductor quantum wires and dots to artificial crystals with exotic electronic properties including carbon nanotubes as an example. The purpose of this review is to discuss some examples of recent developments and the future outlook in the investigation of transport properties of these systems.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126030263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An adaptive grid approach for the simulation of electromigration induced void migration 一种模拟电迁移诱导空洞迁移的自适应网格方法
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034566
H. Ceric, S. Selberherr
{"title":"An adaptive grid approach for the simulation of electromigration induced void migration","authors":"H. Ceric, S. Selberherr","doi":"10.1109/SISPAD.2002.1034566","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034566","url":null,"abstract":"For tracking electromigration induced evolution of voids a diffuse interface model is applied. We assume an interconnect as two-dimensional electrically conducting via which contains initially a circular void. The diffuse interface governing equation was solved applying a finite element scheme with a robust local grid adaptation algorithm. Simulations were carried out for voids exposed to high current.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121990336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Three-dimensional triangle-based simulation of etching processes 基于三维三角形的蚀刻过程模拟
International Conferencre on Simulation of Semiconductor Processes and Devices Pub Date : 2002-11-07 DOI: 10.1109/SISPAD.2002.1034533
O. Lenhart, E. Bar
{"title":"Three-dimensional triangle-based simulation of etching processes","authors":"O. Lenhart, E. Bar","doi":"10.1109/SISPAD.2002.1034533","DOIUrl":"https://doi.org/10.1109/SISPAD.2002.1034533","url":null,"abstract":"A software module for the three-dimensional simulation of etching processes has been developed. It works on multilayer structures given as triangulated surface meshes. The mesh is moved no dewise according to rates which in this work have been determined from isotropic and anisotropic components. An important feature of the algorithm is the automatic detection of triple lines along mask edges and the refinement of triangles at these triple lines. This allows for the simulation of underetching. The capabilities of the algorithm are demonstrated by examples such as the simulation of glass etching for the fabrication of a phase shift mask for optical lithography and the etching of an STI trench structure.","PeriodicalId":249609,"journal":{"name":"International Conferencre on Simulation of Semiconductor Processes and Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129938397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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