2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)最新文献_第4页

Low-power FFT via reduced precision redundancy 低功率FFT通过降低精度冗余

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI: 10.1109/SIPS.2001.957337

S. Sridhara, Naresh R Shanbhag

引用次数: 6

SystemC based architecture exploration of a 3D graphic processor 基于SystemC的三维图形处理器架构探索

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI: 10.1109/SIPS.2001.957344

Tim Kogel, Andreas Wieferink, H. Meyr, A. Kroll

{"title":"SystemC based architecture exploration of a 3D graphic processor","authors":"Tim Kogel, Andreas Wieferink, H. Meyr, A. Kroll","doi":"10.1109/SIPS.2001.957344","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957344","url":null,"abstract":"We propose a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable system architecture model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. We have applied this methodology to a 100 million gate design of a 3D graphic processor. We were able to demonstrate the feasibility and define the final system architecture within 2 months. This 3D processor implements the ray-tracing rendering paradigm on one chip allowing real time rendering of 3D scenes with photo-realistic quality. Based on the results of this case study, we present the benefits of our methodology to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Implementation of an efficient FIR filter chip for PRML read channels 用于PRML读通道的高效FIR滤波器的实现

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI: 10.1109/SIPS.2001.957348

J. Kang, B. G. Jo, M. Sunwoo

引用次数: 0

DSP implementation of low computational 3D sound localization algorithm DSP实现低计算量的三维声音定位算法

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI: 10.1109/SIPS.2001.957336

N. Sakamoto, W. Kobayashi, T. Onoye, I. Shirakawa

引用次数: 8

An efficient shape coding scheme and its codec design 一种高效的形状编码方案及其编解码器设计

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI: 10.1109/SIPS.2001.957351

Y. Hwang, Yun-Chiang Wang, Shi-Shen Wang

引用次数: 19

A catastrophic error mode in adaptive predictive DIR equalisation of dynamic channels 动态信道自适应预测DIR均衡中的灾难性误差模式

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI: 10.1109/SIPS.2001.957345

M. Boyle, A. Fagan

{"title":"A catastrophic error mode in adaptive predictive DIR equalisation of dynamic channels","authors":"M. Boyle, A. Fagan","doi":"10.1109/SIPS.2001.957345","DOIUrl":"https://doi.org/10.1109/SIPS.2001.957345","url":null,"abstract":"The use of a linear equaliser to shorten the impulse response of a channel to a shorter desired impulse response (DIR) prior to a Viterbi algorithm (VA) detection of the data is a well-known technique. Also OFDM systems often require channel truncation. It has previously been shown that for dynamic channels it is beneficial to operate a number of equalisers in parallel, each targeted on a different DIR. Each equaliser is followed by an individual VA. A simple decision rule is used to select which of the VA outputs is presented as the actual decision. We refer to this strategy as switched DIR equalisation. A catastrophic error mode is observed in the operation of adaptive DIR systems in slowly varying channels. This error mode causes the equaliser to become severely maladjusted. The system cannot spontaneously recover from this situation. This paper reviews the switched DIR equalisation system and explains the mechanism underlying the error mode in the adaptive DIR system. Simulation results are presented that indicate the efficacy of the dual switched DIR MLSE-VA to operate successfully in comparison to adaptive DIR MLSE-VA systems in time varying frequency selective Rayleigh fading channels.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122225729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

High speed downlink packet access (HSDPA)-the path towards 3.5G 高速下行分组接入(HSDPA)——迈向3.5G的路径

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI: 10.1109/SIPS.2001.957361

P. Mogensen

引用次数: 3

Efficient implementation of low bit rate 1.6 Kbps speech coder using field programmable gate arrays 使用现场可编程门阵列高效实现低比特率1.6 Kbps语音编码器

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 2001-09-26 DOI: 10.1109/SIPS.2001.957343

Han-Chiang Chen

引用次数: 2

VLSI implementation-oriented (3, k)-regular low-density parity-check codes 面向VLSI实现的(3,k)规则低密度奇偶校验码

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2001.957328

Tong Zhang, K. Parhi

引用次数: 82

Analysis of wavelet transform implementations for image and texture coding applications in programmable platforms 小波变换在图像和纹理编码中的应用分析

2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578) Pub Date : 1900-01-01 DOI: 10.1109/SIPS.2001.957355

Y. Andreopoulos, P. Schelkens, J. Cornelis

引用次数: 12