{"title":"基于SystemC的三维图形处理器架构探索","authors":"Tim Kogel, Andreas Wieferink, H. Meyr, A. Kroll","doi":"10.1109/SIPS.2001.957344","DOIUrl":null,"url":null,"abstract":"We propose a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable system architecture model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. We have applied this methodology to a 100 million gate design of a 3D graphic processor. We were able to demonstrate the feasibility and define the final system architecture within 2 months. This 3D processor implements the ray-tracing rendering paradigm on one chip allowing real time rendering of 3D scenes with photo-realistic quality. Based on the results of this case study, we present the benefits of our methodology to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"SystemC based architecture exploration of a 3D graphic processor\",\"authors\":\"Tim Kogel, Andreas Wieferink, H. Meyr, A. Kroll\",\"doi\":\"10.1109/SIPS.2001.957344\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable system architecture model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. We have applied this methodology to a 100 million gate design of a 3D graphic processor. We were able to demonstrate the feasibility and define the final system architecture within 2 months. This 3D processor implements the ray-tracing rendering paradigm on one chip allowing real time rendering of 3D scenes with photo-realistic quality. Based on the results of this case study, we present the benefits of our methodology to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.\",\"PeriodicalId\":246898,\"journal\":{\"name\":\"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2001.957344\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2001.957344","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SystemC based architecture exploration of a 3D graphic processor
We propose a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable system architecture model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. We have applied this methodology to a 100 million gate design of a 3D graphic processor. We were able to demonstrate the feasibility and define the final system architecture within 2 months. This 3D processor implements the ray-tracing rendering paradigm on one chip allowing real time rendering of 3D scenes with photo-realistic quality. Based on the results of this case study, we present the benefits of our methodology to define successively a feasible system architecture coping with the processing and memory bandwidth requirements.