Implementation of an efficient FIR filter chip for PRML read channels

This paper proposes a low power and area efficient FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels, which is a 6-b, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of four pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter chip, using the 0.65 /spl mu/m technology, dissipates 120 mW at 100 Hz, uses the 3.3 V power supply and occupies 1.88/spl times/1.38 mm/sup 2/. The chip shows about 11% power reduction and about 15% area reduction compared with existing architectures. This chip was fabricated by Hyundai Semiconductor.