ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference最新文献

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An impedance-tracking battery-less arbitrary-waveform neurostimulator with load-adaptive 20V voltage compliance 具有负载自适应20V电压顺应性的阻抗跟踪无电池任意波形神经刺激器
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598283
Hossein Kassiri, Gairik Dutta, N. Soltani, Chang Liu, Yu Hu, R. Genov
{"title":"An impedance-tracking battery-less arbitrary-waveform neurostimulator with load-adaptive 20V voltage compliance","authors":"Hossein Kassiri, Gairik Dutta, N. Soltani, Chang Liu, Yu Hu, R. Genov","doi":"10.1109/ESSCIRC.2016.7598283","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598283","url":null,"abstract":"A 4-channel wireless and battery-less neurostimulator with impedance-tracking power-adaptive voltage compliance is presented. The device houses a 10 mm2 0.35μm HV-CMOS SoC (system on a chip) that performs current-mode arbitrary-waveform stimulation with voltage compliance of up to 20 V. An on-chip mixed-signal controller together with a 3-bit charge-pump maintain supply voltage at its minimum required value, resulting in up to 68.5% saving in power. An 8-bit current DAC is implemented in each channel, which together with adjustable supply voltage yield a current range from 23 μA to 95 mA (100Ω load). The device receives both power and configuration commands wirelessly using a near-field inductive link. The neurostimulator SoC is wire-bonded on a 2×2 cm2 PCB. Additional rigid and flexible PCBs of the same size provide wireless command and power interface. The 3-board 2×2×0.7 cm3 stacked system weighs 6 grams.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124470894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An 18Gbps polymer microwave fiber (PMF) communication link in 40nm CMOS 40nm CMOS中18Gbps聚合物微波光纤(PMF)通信链路
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598346
Niels Van Thienen, Yang Zhang, Maxime De Wit, P. Reynaert
{"title":"An 18Gbps polymer microwave fiber (PMF) communication link in 40nm CMOS","authors":"Niels Van Thienen, Yang Zhang, Maxime De Wit, P. Reynaert","doi":"10.1109/ESSCIRC.2016.7598346","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598346","url":null,"abstract":"A high-speed polymer microwave fiber (PMF) communication link is implemented in a 40nm bulk CMOS technology, by making use of two-tone CP-FSK modulation and a carrier frequency of 120GHz. The presented transceiver and enhanced coupler, with a loss of only 3.4dB, allows communication over a distance of 15m at 1.5Gbps. Data rates up to 17.7Gbps were achieved over a link distance of 1m with a BER <; 10-12. The maximum product of data rate and distance is 60.8Gbps.m over a distance of 8m, resulting in an energy efficiency of only 1.2pJ/bit/m. The transmitter has an output power level of -1.9dBm at 120GHz and a DC power consumption of 11.1mW, the receiver consumes 59.6mW. The transmitter and receiver occupy an active area of respectively 0.025mm2 and 0.43mm2 in 40nm CMOS.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123325262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Bang-bang digital PLLs 砰砰数字锁相环
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598309
S. Levantino
{"title":"Bang-bang digital PLLs","authors":"S. Levantino","doi":"10.1109/ESSCIRC.2016.7598309","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598309","url":null,"abstract":"This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity. It will be also demonstrated that this property can be generalized to the case of PLLs based on coarse time-to-digital converters with mid-rise quantization, whose adoption speeds up lock transients. The results are assessed in a fabricated 3.6-GHz fractional-N digital phase-locked loop.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125354295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 9.8b-ENOB 5.5fJ/step fully-passive compressive sensing SAR ADC for WSN applications 用于WSN应用的9.8b-ENOB 5.5fJ/阶跃全无源压缩感知SAR ADC
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598250
Wenjuan Guo, Nan Sun
{"title":"A 9.8b-ENOB 5.5fJ/step fully-passive compressive sensing SAR ADC for WSN applications","authors":"Wenjuan Guo, Nan Sun","doi":"10.1109/ESSCIRC.2016.7598250","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598250","url":null,"abstract":"The emerging compressive sensing (CS) theory states that the sparsity of a signal can be exploited to reduce the ADC conversion rate. However, most previous CS frameworks still require dedicated analog CS encoders in front-of low-rate ADCs. Differently, this work proposes a fully-passive CS framework that directly embeds CS into a conventional SAR ADC, reducing the ADC power by 4 times. A prototype chip is fabricated in a 0.13μm CMOS process. Discrete-tone signals are converted and reconstructed with a peak SNDR of 61dB and a maximum signal sparsity of 8.2%. A 1-second long speech signal is also used to demonstrate the capability of the chip to compressively sense real-world signals. At 0.8V and 1MS/s, the CS-SAR ADC consumes 19.2μW in the Nyquist mode and 5μW in the CS mode. The peak FoM in the CS mode is 5.5fJ/step.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116876751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of broadband mm-wave and THz frequency doublers 宽带毫米波和太赫兹倍频器的设计
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598318
Hamidreza Aghasi, E. Afshari
{"title":"Design of broadband mm-wave and THz frequency doublers","authors":"Hamidreza Aghasi, E. Afshari","doi":"10.1109/ESSCIRC.2016.7598318","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598318","url":null,"abstract":"Wideband high power generation is an essential and challenging part of many Terahehrtz systems. In this paper we review some of our recent demonstrations of Si/SiGe THz frequency multipliers that generate a wideband high power signal. The proposed design techniques blend the nonlinear modeling of the active device with new circuit topologies and high efficiency microwave structures. In the first prototype, using a 130-nm SiGe HBT process (fmax=280GHz), a wideband frequency doubler operating from 430 to 510 GHz is designed. The active doubler generates an unsaturated output power of -8.2 dBm, corresponding to 16.2 dB of conversion loss. The second circuit is a 220-275 GHz travelling wave frequency multiplier, which achieves a 3-dB bandwidth of 7.8% with a saturated output power of -6.6 dBm in a 65 nm bulk CMOS technology. The last circuit is a passive frequency doubler, based on a 65 nm bulk CMOS process. This doubler also achieves a high output power of -6.3 dBm at 478 GHz and a simulated bandwidth of 70 GHz.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121288754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 0.2–11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOS 一种基于28nm FDSOI CMOS的0.2-11.7GHz高精度注入锁定多相发生器,具有混合模拟/数字校准环路
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598310
G. Anzalone, E. Monaco, G. Albasini, S. Erba, A. Mazzanti
{"title":"A 0.2–11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOS","authors":"G. Anzalone, E. Monaco, G. Albasini, S. Erba, A. Mazzanti","doi":"10.1109/ESSCIRC.2016.7598310","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598310","url":null,"abstract":"An injection-locked ring oscillator (ILRO) leveraging mixed analog/digital calibration loops for high-accuracy 8-phase clock generation is proposed. A phase detector (PD) based on passive mixers measures the quadrature error and continuously tunes the oscillator for fine phase correction. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. The ILRO maintains high phase accuracy over a wide operation frequency range and large supply and temperature variations. The chip is fabricated in 28nm FDSOI CMOS and with power consumption from 3mW to 15mW, measurements demonstrate a 0.2-11.7GHz frequency range with better than 1.5° quadrature phase error over ±20% supply and -40×120°C temperature variations. Measured performances meet the requirements of 1-to-45Gb/s quarter-rate multi-standard I/O receivers.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116568312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Register file circuits and post-deployment framework to monitor aging effects in field 注册文件电路和部署后框架,以监测现场老化效应
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598332
Teng Yang, P. Kinget, Mingoo Seok
{"title":"Register file circuits and post-deployment framework to monitor aging effects in field","authors":"Teng Yang, P. Kinget, Mingoo Seok","doi":"10.1109/ESSCIRC.2016.7598332","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598332","url":null,"abstract":"This paper presents novel 6-T SRAM register file (RF) circuits and in-field framework for managing chip's lifetime after deployment. Our proposed RF circuits can in-situ sense threshold voltages (Vt) of all six transistors of every bitcell in an RF robustly against temperature variations. This allows us (1) to monitor aging effects of both NMOS and PMOS such as negative and positive bias temperature instabilities (NBTI, PBTI) and (2) to monitor those in the post deployment condition where environmental parameters, notably temperature, cannot be easily controlled. Using these sensed Vt's, our proposed post-deployment framework can estimate critical circuit-level parameters of an RF such as data retention voltage (DRV) and read access time (TACC). After chip's deployment, our proposed sensing circuits and framework can be periodically (e.g., every month) exercised to diagnose the reliability of an RF through chip's lifetime. We can use the results of the diagnosis to potentially trigger countermeasures. The area overhead of adding our proposed sensing capability to a 32×32b RF is 8.5%.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127493900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI 一个128 kb单线8.4 fJ/bit 90MHz, 0.3V 7T无感测放大器的28 nm FD-SOI SRAM
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598333
B. Mohammadi, O. Andersson, J. Nguyen, L. Ciampolini, A. Cathelin, J. Rodrigues
{"title":"A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI","authors":"B. Mohammadi, O. Andersson, J. Nguyen, L. Ciampolini, A. Cathelin, J. Rodrigues","doi":"10.1109/ESSCIRC.2016.7598333","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598333","url":null,"abstract":"In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240mV and the retention voltage is found at 200mV.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127435158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation 使用静态偏置预估,ARM Cortex®-A53的静态功率提高30%
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598237
F. Abouzeid, C. Bernicot, S. Clerc, J. Daveau, G. Gasiot, D. Noblet, Dimitri Soussan, P. Roche
{"title":"30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation","authors":"F. Abouzeid, C. Bernicot, S. Clerc, J. Daveau, G. Gasiot, D. Noblet, Dimitri Soussan, P. Roche","doi":"10.1109/ESSCIRC.2016.7598237","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598237","url":null,"abstract":"This paper presents an energy efficiency improvement methodology based on the use of additional static biasing instead of margins during design stage. While the impact of margins used to prevent unsystematic process limitations cannot be recovered after fabrication, using biasing anticipation offers the possibility to enable the degradation recovery only when it is required. A CAD study on ARM Cortex®-M4 Microcontrollers (MCU) showed up to 50% of static current reduction at typical corner, nominal voltage, compared to the margin-based methodology. An implementation of a 1GHz ARM Cortex®-A53 core in 28nm fully-depleted silicon-on-insulator (FD-SOI) was performed using this methodology, and silicon measurements on 60 dies confirmed up to 30% median static power improvements.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133551435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic system 用于大规模神经形态系统的高可调谐65纳米CMOS LIF神经元
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference Pub Date : 2016-09-01 DOI: 10.1109/ESSCIRC.2016.7598245
Syed Ahmed Aamir, Paul Müller, Andreas Hartel, J. Schemmel, K. Meier
{"title":"A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic system","authors":"Syed Ahmed Aamir, Paul Müller, Andreas Hartel, J. Schemmel, K. Meier","doi":"10.1109/ESSCIRC.2016.7598245","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2016.7598245","url":null,"abstract":"We present the design and measurement of a continuous-time, accelerated, reconfigurable Leaky Integrate and Fire (LIF) neuron model emulated in 65-nm CMOS technology. The neuron circuit is designed as a sub-circuit of our highly integrated neuromorphic prototype chip, the “HICANN-DLS”. The design is geared towards testability and debug features, as well as area and power efficiency. Each neuron in the array integrates current from a multitude of input synapses onto an RC integrator within the synaptic input sub-circuit, where a variable resistor tunes the synaptic time constant. Linear transconductors convert voltage into an equivalent current as well as modeling the leak term, while a pulse generator circuit evokes a digital spike event. Our measurements show that the neuron successfully integrates input synaptic events ranging from a few nA to greater than 10 µA and tunes a wide range of tunable synaptic and membrane time constants. A higher membrane dynamic range of up to 1100 mV, and longer refractory times can be achieved, operating 1000 times faster than biological real-time. The design of the neuron simplifies calibration and reduces the mismatch, as multiple die measurements indicate. We demonstrate a one-to-one correspondence to software simulation for a typical computational model neuron. Due to the wide tunable range, the neuron is to be our general-purpose element of our second generation flexible neuromorphic platform for a variety of computational models.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131525675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
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