30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation

Abstract

This paper presents an energy efficiency improvement methodology based on the use of additional static biasing instead of margins during design stage. While the impact of margins used to prevent unsystematic process limitations cannot be recovered after fabrication, using biasing anticipation offers the possibility to enable the degradation recovery only when it is required. A CAD study on ARM Cortex®-M4 Microcontrollers (MCU) showed up to 50% of static current reduction at typical corner, nominal voltage, compared to the margin-based methodology. An implementation of a 1GHz ARM Cortex®-A53 core in 28nm fully-depleted silicon-on-insulator (FD-SOI) was performed using this methodology, and silicon measurements on 60 dies confirmed up to 30% median static power improvements.