B. Mohammadi, O. Andersson, J. Nguyen, L. Ciampolini, A. Cathelin, J. Rodrigues
{"title":"一个128 kb单线8.4 fJ/bit 90MHz, 0.3V 7T无感测放大器的28 nm FD-SOI SRAM","authors":"B. Mohammadi, O. Andersson, J. Nguyen, L. Ciampolini, A. Cathelin, J. Rodrigues","doi":"10.1109/ESSCIRC.2016.7598333","DOIUrl":null,"url":null,"abstract":"In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240mV and the retention voltage is found at 200mV.","PeriodicalId":246471,"journal":{"name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI\",\"authors\":\"B. Mohammadi, O. Andersson, J. Nguyen, L. Ciampolini, A. Cathelin, J. Rodrigues\",\"doi\":\"10.1109/ESSCIRC.2016.7598333\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240mV and the retention voltage is found at 200mV.\",\"PeriodicalId\":246471,\"journal\":{\"name\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2016.7598333\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2016.7598333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI
In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240mV and the retention voltage is found at 200mV.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
