Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)最新文献_第3页

Instruction level test methodology for CPU core software-based self-testing 基于软件的CPU核心自测试的指令级测试方法

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431227

S. Shamshiri, H. Esmaeilzadeh, Z. Navabi

{"title":"Instruction level test methodology for CPU core software-based self-testing","authors":"S. Shamshiri, H. Esmaeilzadeh, Z. Navabi","doi":"10.1109/HLDVT.2004.1431227","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431227","url":null,"abstract":"TIS (S. Shamshiri et al., 2004) is an instruction level methodology for CPU core self-testing that enhances the instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced with test instructions so that online testing can be done with no performance penalty. TIS tests different parts of the CPU and detects stuck-at faults. This method can be employed in offline and online testing of all kinds of processors. Hardware-oriented implementation of TIS was proposed previously (S. Shamshiri et al., 2004) that tests just the combinational units of the processor. Contributions of this paper are first, a software-based approach that reduces the hardware overhead to a reasonable size and second, testing the sequential parts of the processor besides the combinational parts. Both hardware and software oriented approaches are implemented on a pipelined CPU core and their area overheads are compared. To demonstrate the appropriateness of the TIS test technique, several programs are executed and fault coverage results are presented.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122635073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Reference model based RTL verification: an integrated approach 基于参考模型的RTL验证:一种集成方法

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431221

W. Hung, N. Narasimhan

引用次数: 10

Towards an efficient assertion based verification of SystemC designs 对SystemC设计进行有效的基于断言的验证

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431224

A. Habibi, S. Tahar

引用次数: 26

Assertion-based power/performance analysis of network processor architectures 基于断言的网络处理器架构的功率/性能分析

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431261

Jia Yu, Wei Wu, X. Chen, H. Hsieh, Jun Yang, F. Balarin

{"title":"Assertion-based power/performance analysis of network processor architectures","authors":"Jia Yu, Wei Wu, X. Chen, H. Hsieh, Jun Yang, F. Balarin","doi":"10.1109/HLDVT.2004.1431261","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431261","url":null,"abstract":"Network processors (NPUs) have emerged as successful platforms to provide both high performance and flexibility in building powerful routers. With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in NPU development. In this paper, we present an assertion-based methodology for system-level power/performance analysis of network processor designs, which can help designers choose the right architecture features and low power techniques. We write power and performance assertions, based on logic of constraints. Trace checkers and simulation monitors are automatically generated to analyze the power and performance characteristics of the network processor model. Furthermore, we apply a low power technique, dynamic voltage scaling (DVS), to the network processor model, and explore their pros and cons with the assertion-based analysis technique. We demonstrate that the assertion-based methodology is useful and effective for system level power/performance analysis.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132292543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Efficient test-based model generation for legacy reactive systems 为遗留响应系统高效地生成基于测试的模型

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431246

T. Margaria, Oliver Niese, Harald Raffelt, B. Steffen

引用次数: 83

Formal verification of pipelined processors with load-value prediction 带负载值预测的流水线处理器的形式化验证

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431231

M. Velev

{"title":"Formal verification of pipelined processors with load-value prediction","authors":"M. Velev","doi":"10.1109/HLDVT.2004.1431231","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431231","url":null,"abstract":"The formal verification of pipelined processors with load-value prediction is studied. The formal verification is done by abstractions with the logic of equality with uninterpreted functions and memories (EUFM), using an automatic tool flow. Applying special abstractions in previous work had resulted in EUFM correctness formulas where most of the terms (abstract word-level values) appear in only positive equations (equality comparisons) or as arguments of uninterpreted functions and uninterpreted predicates, allowing us to treat such terms as distinct constants - a property we call positive equality. That property resulted in orders of magnitude speedup. However, the mechanism for correcting load-value mispredictions introduces both positive and negated equations between the actual and predicted load values, thus reducing significantly the potential for exploiting positive equality. The contributions of the paper are: 1) modeling and formal verification of a pipelined processor with load-value prediction and a fully implemented mechanism for correcting load-value mispredictions, and comparison with the formal verification of a variant of the design where the load values are not predicted, such that the data hazards are avoided by stalling the dependent instruction; and 2) a way to abstract the mechanism for detecting load-value mispredictions, thus allowing the use of positive equality, at the cost of enriching the specification processor with the abstracted mechanism for detecting load-value mispredictions.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"15 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133357366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

On using a 2-domain partitioned OBDD data structure in verification 在验证中使用2域分区OBDD数据结构

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431234

Tao Feng, Li-C. Wang, K. Cheng, Andy Lin

引用次数: 0

Enhancing the efficiency of Bayesian network based coverage directed test generation 提高了基于贝叶斯网络的覆盖定向测试生成效率

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431241

Markus Braun, S. Fine, A. Ziv

引用次数: 18

Simplifying design and verification for structural hazards and datapaths in pipelined circuits 简化流水线电路中结构危险和数据路径的设计和验证

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431229

Jason T. Higgins, M. Aagaard

引用次数: 2

Functional verification based on the EFSM model 基于EFSM模型的功能验证

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431240

F. Fummi, C. Marconcini, G. Pravadelli

引用次数: 8