Towards an efficient assertion based verification of SystemC designs

Abstract

In this paper, we present an approach to verify efficiently assertions added on top of the SystemC library and based on the property specification language (PSL). In order to improve the assertion coverage, we also propose an approach based on both static code analysis and genetic algorithms. Static code analysis will help generate a dependency relation between inputs and assertion parameters as well as define the ranges of inputs affecting the assertion. The genetic algorithm will optimize the test generation to get more efficient coverage of the assertion. Experimental results illustrate the efficiency of our approach compared to random simulation.