Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)最新文献

On code coverage measurement for Verilog-A 关于Verilog-A的代码覆盖率度量

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431251

Y. Sha, M. Lee, C. Liu

引用次数: 4

Effects of property ordering in an incremental formal modeling methodology 增量形式化建模方法中属性排序的影响

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431245

S. Suhaib, D. Mathaikutty, S. Shukla

{"title":"Effects of property ordering in an incremental formal modeling methodology","authors":"S. Suhaib, D. Mathaikutty, S. Shukla","doi":"10.1109/HLDVT.2004.1431245","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431245","url":null,"abstract":"In this paper, we analyze the effect of ordering linear time properties while using the Extreme Formal Modeling (XFM) methodology in building \"prescriptive formal models\" (PFM). PFMs are formal models built incrementally by adding user stories and are used as specification golden models. In our methodology, the user stories are captured in Linear Time Temporal Logic (LTL). A more expressive logic or formalism could be used for describing the user stories as well. During incremental model building, the PFMs often blow up in size in terms of the state space, and the main tenet of XFM being regressive model checking, blown up models often make it impossible to carry out the XFM methodology. Here, we propose property ordering hueristics to circumvent this problem. We compare these hueristics with: (i) no specific ordering of user stories (standard approach), (ii) sorting of the user stories based on a weighting scheme (property based sorting), and (Hi) predicate based sorting of user stories based on an eliminative scheme (predicate based sorting). We show that the predicate based sorting scheme is the most effective way to carry-out XFM model building. We illustrate the schemes and the comparison by modeling a monitor for the ISA bus and for the arbitration phase of Pentium Pro processor's bus using the Cadence SMV. We also provide an algorithm for the predicate based sorting that yields the best control on the increments in model size.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131469520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Test quality for high level structural test 高水平结构试验质量

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431250

Ahmad A. Al-Yamani, E. McCluskey

引用次数: 5

What happened to the intelligent test bench? 智能测试台怎么了?

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431272

Gary Smith

引用次数: 0

On identifying functionally untestable transition faults 关于识别功能上不可测试的转换错误

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431252

Xiao Liu, M. Hsiao

引用次数: 8

On equivalence checking between behavioral and RTL descriptions 行为描述与RTL描述的等价性检验

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431267

M. Fujita

引用次数: 6

Model validation for mapping specification behaviors to processing elements 将规范行为映射到处理元素的模型验证

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431247

S. Abdi, D. Gajski

引用次数: 1

High level hardware validation using hierarchical message sequence charts 使用分层消息序列图的高级硬件验证

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431265

P. Murthy, S. Rajan, K. Takayama

引用次数: 5

Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques 处理器隐藏寄存器对故障注入技术精度的影响分析

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431266

D. Gil, J. Gracia, J. Baraza, P. Gil

{"title":"Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques","authors":"D. Gil, J. Gracia, J. Baraza, P. Gil","doi":"10.1109/HLDVT.2004.1431266","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431266","url":null,"abstract":"Modern processors tend to increase the number of registers, being part of them not accessible by the instruction set. Traditionally, the effect of faults in these hidden registers has not been considered during system validation using fault injection. In this paper, a study of the importance of faults in hidden registers is performed. Firstly, we have analysed the sensitivity of hidden registers to faults in combinational logic. In a second phase, we have analysed the impact of the faults occurred in hidden registers on system behaviour. A broad set of permanent and transient faults have been injected into the models of two typical commercial microcontrollers, using a VHDL-based fault injection tool developed by our research group. The results obtained indicate that the incidence of hidden registers is not negligible, and in some cases is even notable. This fact suggests that widely used fault injection techniques such as SWIFI could not be enough to perform a full and representative validation of modern processors, and it would be necessary to complement with other fault injection techniques that have a higher degree of accessibility.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129602870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Dynamic guiding of bounded property checking 有界属性检查的动态引导

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI: 10.1109/HLDVT.2004.1431223

P. Peranandam, R. Weiss, Jürgen Ruf, T. Kropf, W. Rosenstiel

{"title":"Dynamic guiding of bounded property checking","authors":"P. Peranandam, R. Weiss, Jürgen Ruf, T. Kropf, W. Rosenstiel","doi":"10.1109/HLDVT.2004.1431223","DOIUrl":"https://doi.org/10.1109/HLDVT.2004.1431223","url":null,"abstract":"Current statistics attribute up to 75% of the overall design costs of digital hardware and embedded system development to the verification task. In recent years, the trend to augment functional with formal verification tries to alleviate this problem. Efficient property checking algorithms allow automatic verification of middle-sized designs nowadays. However, the steadily increasing design sizes still leave verification the major bottleneck, because formal methodologies do not yet scale to very large designs. In this paper we present the formal verification tool SymC based on forward state space traversal and so-called AR-automata for property checking, both internally represented with BDDs. Furthermore, we introduce a new methodology called dynamic guiding. This methodology best suits multimodule concurrent finite state machine (FSM) designs. The aim of guiding is to reduce the intermediate and final BDD size, which in turn makes this verification technique applicable to larger designs. Our approach exploits abstract information of the design in the form of regular expressions and effectively guides the symbolic traversal depending on the verified property.","PeriodicalId":240214,"journal":{"name":"Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131355119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6