Model validation for mapping specification behaviors to processing elements

Abstract

Increase in system level modeling has given rise to a need for efficient functional validation of models above cycle accurate level. This paper presents a technique for checking functional equivalence of system level models, before and after the distribution of behaviors in the specification over components in the platform architecture. We derive a control flow graph from models written in system level design languages (SLDLs) and reduce it to a normal form representation using well defined rules. Two models having identical normal form are shown to be functionally equivalent. An equivalence checker based on the above concept is used to automatically check if the architecture level model is functionally equivalent to the specification model. As a result, the models generated for various mapping decisions do not have to be reverified using costly simulations.