Instruction level test methodology for CPU core software-based self-testing

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI:10.1109/HLDVT.2004.1431227

S. Shamshiri, H. Esmaeilzadeh, Z. Navabi

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引用次数: 5

Abstract

TIS (S. Shamshiri et al., 2004) is an instruction level methodology for CPU core self-testing that enhances the instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced with test instructions so that online testing can be done with no performance penalty. TIS tests different parts of the CPU and detects stuck-at faults. This method can be employed in offline and online testing of all kinds of processors. Hardware-oriented implementation of TIS was proposed previously (S. Shamshiri et al., 2004) that tests just the combinational units of the processor. Contributions of this paper are first, a software-based approach that reduces the hardware overhead to a reasonable size and second, testing the sequential parts of the processor besides the combinational parts. Both hardware and software oriented approaches are implemented on a pipelined CPU core and their area overheads are compared. To demonstrate the appropriateness of the TIS test technique, several programs are executed and fault coverage results are presented.

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基于软件的CPU核心自测试的指令级测试方法

TIS (S. Shamshiri et al.， 2004)是一种用于CPU核心自我测试的指令级方法，它通过测试指令来增强CPU的指令集。由于测试指令的功能与NOP指令相同，因此可以用测试指令替换NOP指令，这样就可以在没有性能损失的情况下进行在线测试。TIS测试CPU的不同部分并检测卡在故障上。该方法可用于各种处理器的离线和在线测试。以前提出了面向硬件的TIS实现(S. Shamshiri et al.， 2004)，它只测试处理器的组合单元。本文的贡献在于:首先，基于软件的方法将硬件开销降低到合理的大小;其次，除了组合部分之外，还测试了处理器的顺序部分。面向硬件和面向软件的方法都是在一个流水线的CPU核心上实现的，并比较了它们的面积开销。为了证明TIS测试技术的适用性，执行了几个程序并给出了故障覆盖率结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

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