Functional verification based on the EFSM model

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI:10.1109/HLDVT.2004.1431240

F. Fummi, C. Marconcini, G. Pravadelli

引用次数: 8

Abstract

The paper presents a methodology for addressing hard-to-detect faults when a high-level ATPG is applied to verify functional descriptions of sequential circuits. A particular kind of extended finite state machines is adopted to improve detectability of such faults.

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基于EFSM模型的功能验证

本文提出了一种解决高级ATPG用于验证顺序电路功能描述时难以检测故障的方法。采用一种特殊的扩展有限状态机来提高这类故障的可检测性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

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