2008 IEEE International Conference on Electron Devices and Solid-State Circuits最新文献

{"title":"National project on 45 to 32 nm metal oxide semiconductor field effect transistors for next century IC fabrications","authors":"H. Hwang, C.W. Wang, K. Chang, C. Tsai, K. Leou, K. Chang-Liao, Chun-Chang Lu, S.C. Chang, F. Chiu, C.H. Liu, A. Chin, Kow-Ming Chang, Bwo-Ning Chen","doi":"10.1109/EDSSC.2008.4760691","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760691","url":null,"abstract":"It is well known that the Taiwan Semiconductor industries play the very key roles for the worldwide IC foundry, and the advanced research of nanoelectronics is the lifeline for its long term developments. Professor Huey-liang Hwang effectively integrated the most outstanding research team and resource in Taiwan on the National Project on Nanometer CMOS Transistors for the 21 century, which is sponsored by the Ministry of Economic Affairs of ROC. A dozen of Professors from NTHU( National Tsing Hua University) with expertise at the novel materials and analysis and NCTU( National Chiao Tung University) with expertise at devices and reliability are devoted to the studies and are in collaboration with the world-wide-known company such as TSMC, and breakthrough of the key technologies of 45-32 nm technologies are achieved. The objective of this project is focused on the development of advanced metal gate/high-k MOSFET for 45 nm node generation and beyond, the efforts include the world first successful suppression the oxide/Si interfacial layer formation by using a bi-layer composite of HfO2 3.2 nm (ALD)/HfO2 1.5 nm (MBE), the results show a dielectric constant of 16 and an EOT of 1.15 nm, a Dit was estimated to be 4.6times1011 cm-2eV-1 with the leakage at Vfb-1V being 8.5times10-6 A/cm2. Also, the thermal stability of HfO2, HfAlOx alloy and Al2O3/HfO2 stack, prepared by ALD were compared, the incorporation of Al in alloy form gave superior characteristics by retaining an amorphous structure up to 1000 C, which suppress the leakage current and retards growth of the interfacial layer giving the least increment of EOT and interface traps. Besides, by incorporating Al into TiO2 gave an EOT value of the Al2O3/TiAlOx/Al2O3 film down to 0.8 nm. Furthermore, high selectivity was obtained via etching the HfAlO and silicon wafer with pattern using the ICP Plasma. In this project, YbSi metal gate for n-MOSFET and IrSi metal gate p-MOSFET were successfully fabricated for the HfAlON MESFET. The results showed the good effective workfunction of 4.15 and 4.9 eV and no degradation of gate dielectric current and mobility in the YbxSi/ HfAlON and IrxSi/ HfAlON FUSI-gates by reducing the metal diffusion at lower temperatures.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131316133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimized CML circuits for 10-Gb/s backplane transmission with 120-nm CMOS technology","authors":"Bo Wang, Dianyong Chen, A. Liao, B. Liang, T. Kwasniewski","doi":"10.1109/EDSSC.2008.4760694","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760694","url":null,"abstract":"In this paper, we discuss an optimized current-mode logic (CML) circuit design technique for high-speed backplane transmission. The inductorless CML circuits are extensively used in high-speed digital circuits. With a given CMOS technology, the CML circuits can be optimally biased for higher speed operation with the considerations of speed, swing, power, load capacitance and area. Typical high-speed CML buffer and latch for 10-Gb/s transmission are designed with the optimized biasing technique with lower power consumption, and compact area (buffer: 10.2 times 14.4 mum2, latch: 30.4 times 32.8 mum2).","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115266250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4-GHz VCO for Multiband OFDM UWB systems","authors":"C. Chan, Siu-Kei Tang, K. Pun","doi":"10.1109/EDSSC.2008.4760742","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760742","url":null,"abstract":"A 4-GHz VCO for Multiband OFDM ultra-wide-band system is presented. Methods for maintaining a good phase noise under reasonable power consumption for the 4 GHz VCO are presented. The design was fabricated in 0.18-mum CMOS process. The measured VCO phase noise at 1 MHz offset from 4 GHz is lower than -126 dBc/Hz at 1.5 V supply voltage and is lower than -120 dBc/Hz even at 1 V supply. The VCO has an output frequency range from 3.1-GHz to 4.1-GHz, and consumes 4.7 mW at 1.5V.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124520902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ZnO nanowire-based oxygen gas sensor","authors":"C. Lu, S. Chang, S. Chang","doi":"10.1109/EDSSC.2008.4760698","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760698","url":null,"abstract":"We report growth of vertically well-aligned ZnO nanowires on ZnO:Ga/glass templates and the fabrication of resistive ZnO nanowire-based oxygen gas sensor. It was found that the ZnO nanowires are grown preferred oriented in the (002) direction with a small X-ray diffraction full-width-half-maximum. From high resolution transmission electron microscopy, scanning electron microscopy and micro-Raman measurements, it was found that the ZnO nanowires prepared in this study are single crystalline with good crystal quality. It was also found that measured sample resistance increased logarithmically as the oxygen gas pressure in the chamber was increased. Such a relationship suggests that the device is potentially useful for resistive oxygen gas sensing at room temperature.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123380095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of uniaxial strain on the gate capacitance of double gate MOSFETs","authors":"M.I. Bin Shams, M.K. Alam, Q. Khosru","doi":"10.1109/EDSSC.2008.4760706","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760706","url":null,"abstract":"Gate capacitance versus voltage (C-V) characteristics for double gate MOSFETs with uniaxially strained silicon substrate are presented incorporating wave function penetration effect. Changes in capacitance with stress levels up to 5 GPa are studied. Physical insights of the capacitance value change are also discussed. Contributions of band splitting and effective mass change in C-V due to uniaxial strain are analyzed. Dependencies of C-V change on doping density and body thickness for uniaxial strain are revealed for double gate MOSFETs.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129440199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling nanoscale MOSFETs by a neural network approach","authors":"Min Fang, Jin He, Jian Zhang, Lining Zhang, M. Chan, Chenyue Ma","doi":"10.1109/EDSSC.2008.4760660","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760660","url":null,"abstract":"This paper presents modeling nanometer MOSFETs by a neural network approach. The principle of this approach is firstly introduced and its application in modeling DC and conductance characteristics of nano-MOSFET is demonstrated in details. It is shown that this approach does not need parameter extraction routine while its prediction of the transistor performance has a small relative error within 1% compared with measure data, thus its result is as accurate as that BSIM model.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125576313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low insertion loss GaAs pHEMT switch utilizing highly n+-doping AlAs etching stop layer design","authors":"D. Lin, F. Chien, Chih-Wei Yang, H. Chiu","doi":"10.1109/EDSSC.2008.4760644","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760644","url":null,"abstract":"This study reports, for the first time, AlGaAs/InGaAs/AlGaAs high-electron mobility transistors (HEMTs) devices and single-pole-single-throw (SPST) switches with utilizing n+-type doping on etching stop AlAs layer (M-HEMTs) designs were fabricated and investigated. We doping on etching stop AlAs layer to reduce parasitic resistances and enhance device DC and RF power performance. These modified M-HEMTs(HEMTs) demonstrated an Sheet resistance (Rsh) is 65.9 Ohms/sq(71.9 Ohms/sq), maximum Ids is 317.8 mA/mm(290.3 mA/mm), transconductance(gm) is 259.3 mS/mm(252.1 mS/mm), cut-off frequency(fT) and maximum frequency(fmax) are 19.4 GHz(18.1 GHz) and 58.6 GHz(45.9 GHz), a power-added efficiency of 33.4 %(30.6 %), and a linear power gain of 13.1 dB(10.3 dB) for an 1.0 mum gate-long device under a 2.4 GHz operation. In addition, both off-state capacitance and the specific on-resistance (Ron) of HEMT are dominated factors which are sensitive to doping n+-type on etching stop layer for RF switch applications. The SPST switches on-state an insertion loss of 1.42 dB(1.68 dB), the off-state an isolation of 13.02 dB(11.42 dB). These characteristics suggest that utilizing n+-type doping on etching stop AlAs layer provide a better device and switches performances improvement.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116386191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"InGaAs and graphene as high mobility channels for post Si-CMOS applications","authors":"P. Ye","doi":"10.1109/EDSSC.2008.4760751","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760751","url":null,"abstract":"The continuous device scaling and performance improvements required by the International Technology Roadmap of Semiconductors (ITRS) are facing a grand challenge as conventional Si CMOS scaling comes to its fundamental physical limits. We review the research progress recently at Purdue University using In-rich InGaAs and epitaxial graphene on SiC as the novel channel materials for post Si CMOS applications suitable for the 15 nm node and beyond.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"38 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116542484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical characteristics and reliability of hafnium oxide films with nitrogen doping","authors":"B. Sen, B.L. Yang","doi":"10.1109/EDSSC.2008.4760707","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760707","url":null,"abstract":"The effects of trace amount of nitrogen doping on the electrical characteristics of thin hafnium oxide have been studied. The chemical compositions and bonding structure of the dielectric film have been explored with x-ray photoelectron spectroscopy (XPS) measurements. Current-voltage (I-V) and capacitance-voltage (C-V) measurements have been conducted on nitrogen-doped hafnium oxide samples and to study the reliability of the film constant-voltage stressing has been performed. The trapping characteristics have been further revealed by conducting the I-V and C-V measurements at different temperatures ranging from 100 to 400 K. We have found that although the deep trap level due to oxygen vacancy and interface trap density due to Hf-Si bonding can be significantly suppressed with nitrogen doping; large amount of shallow traps are still present.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126139922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT Using Pd buried-gate technology","authors":"Chih-Wei Yang, Che-Kai Lin, D. Lin, H. Chiu","doi":"10.1109/EDSSC.2008.4760645","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760645","url":null,"abstract":"In this work, two enhancement-mode (E-mode) GaAs-based high electron mobility transistors (HEMTs), grown by molecular beam epitaxy (MBE) system, have been fabricated and investigated. We evaporated traditional platinum (Pt) and palladium (Pd) as Schottky contact metals to observe high-temperature performance. Following the 1 mum Pt/Ti/Au gate and Pd/Ti/Au gate metals deposition, the devices were thermally annealed at 200degC. Two devices DC and RF performance from 0degC to 100degC were measured. Because the platinum skins into Schottky Layer, the DC and RF characteristics were affected. Experimentally, the palladium gate device showed better DC, RF, and high-temperature characteristics. These advantages suggest that the palladium device is suitable for high-speed and high-power integrated circuit applications.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131763701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}