{"title":"Analog/RF performance analysis of coaxial carbon nanotube MOS field effect transistor from non-equilibrium Green’s function simulation","authors":"Yuchi Che, Y. Tao, Feng Liu, Xingye Zhou, Jin He","doi":"10.1109/EDSSC.2008.4760651","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760651","url":null,"abstract":"Based on the non-equilibrium Greenpsilas function simulation, the analog/RF performance of Coaxial Carbon Nanotube Field Effect Transistor (CNTFET) including the trans-conductance efficiency gm/Id, cutoff frequency ft, and maximum oscillation frequency fmax are analyzed in details. The analysis method is described and the CNTFET analog/RF performance dependence on the operation bias, device chirality, and gate oxide thickness are demonstrated. These results will be useful for the device scientists and circuit engineers to optimize the CNTFET structure and improve its circuit performance for the potential analog/RF application in near future.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131035112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A limiting amplifier with LOS indication for gigabit ethernet","authors":"W.B. Chen, H. Zou, M. Z. Deng, C. Li, L. Deng","doi":"10.1109/EDSSC.2008.4760747","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760747","url":null,"abstract":"The paper presents a high-gain and large-bandwidth limiting amplifier with a maximum data rate of 1.25 Gb/s for Gigabit Ethernet. Composed of a multi-stage amplifier, an output driver, an offset cancellation circuit and a signal-detection circuit, the limiting amplifier provides constant positive-referenced emitter-coupled logic (PECL) output voltage and features a programmable loss-of-signal (LOS) indication and a squelch function that mutes the data output signal when the input voltage falls below the programmable threshold. It is implemented in TSMC 0.35-mum BiCMOS technology, with an active area of 1.3times1.1 mm2. Using a single 3.3-V supply voltage, measured results demonstrate that the input dynamic range is larger than 52 dB and the power consumption is only 60 mW.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133166505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1-GHz LC voltage-controlled oscillator with high linearity and wide range","authors":"W. Tan, Guican Chen, Hong Zhang","doi":"10.1109/EDSSC.2008.4760692","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760692","url":null,"abstract":"A 1-GHz low phase noise LC voltage-controlled oscillator (VCO) with high tuning linearity and wide range is presented. A novel resonant tank with a MOS varactor array and distributed control voltages is proposed to improve the tuning linearity and maintain a wide tuning range. Simulation results show that the tuning nonlinearity of the proposed VCO is only 0.8%, reduced by a factor of 4 compared with a conventional one. The VCO draws 5.2 mA current from a 1.8 V supply and can be tuned from 967 MHz to 1146 MHz (17%). The simulated phase noise is -132.2 dBc@1 MHz for an oscillation frequency of 1056 MHz.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123430543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SPRAM (SPin-transfer torque RAM) Technology for Green IT World","authors":"T. Kawahara, H. Takahashi, H. Ohno","doi":"10.1109/EDSSC.2008.4760631","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760631","url":null,"abstract":"In Green IT world, we could enjoy our daily life with immersed digital equipments that have perfect normally OFF and instant ON functions resulting from environment-conscious technologies. For achieving this, firstly we need a non-volatile RAM technology, namely endowed with non-volatility, infinite number of write cycles, and fast operation at the same time. SPRAM is the most promising solution for this demand.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"954 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122737121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low-power digitally-programmable accurate decibel-linear CMOS VGA for UWB systems","authors":"Bin Jia, Guican Chen, Hong Zhang","doi":"10.1109/EDSSC.2008.4760693","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760693","url":null,"abstract":"A new current-mode circuit for realizing CMOS digitally controlled decibel-linear variable gain amplifier (VGA) is proposed for ultra-wideband systems. The core block of this VGA is a series of programmable current-amplifier cells which are connected by a switch array. Some cells can be cut off under certain gain modes to save the power. Designed in 0.18..m CMOS technology, the VGA provides a 45d B gain range (from 7 dB to 52 dB) with 3 dB per step and a gain error of less than 0.1 dB, and its minimal bandwidth is 285 MHz with a load capacitor of 0.5 pF. The VGA consumes only 6.6-mW on average (from 4.85-8.35 mW), and the range of IIP3 is from -11 dBm to -40 dBm.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124384622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effects of annealing temperature on sensing properties of Pt/HfO2/SiC Schottky-diode hydrogen sensor","authors":"W. Tang, C. Leung, P. Lai","doi":"10.1109/EDSSC.2008.4760752","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760752","url":null,"abstract":"Hafnium oxide (HfO2) is successfully used as gate insulator for fabricating metal-insulator-SiC (MISiC) Schottky-diode hydrogen sensor. Sensors undergone N2 annealing at different temperatures are fabricated for investigation. The hydrogen-sensing properties of these samples are compared with each other by taking the measurements at high temperature under various hydrogen concentrations using a computer-controlled measurement system. Experimental results show that sensitivity increases with the annealing temperature. Higher annealing temperature can enhance the densification of the HfO2 film; improve the oxide stoichiometry; and facilitate the growth of a SiO2 interfacial layer to give better interface quality, thus causing a remarkable reduction of the current of the sensor under air ambient. The effects of hydrogen adsorption on the barrier height and hydrogen-reaction kinetics are also investigated.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115460165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yang Hong, C. Chan, Jianping Guo, Y. Ng, Weiwei Shi, M. Ho, L. Leung, K. Leung, C. Choy, K. Pun
{"title":"Design and challenges of passive UHF RFID tag in 90nm CMOS technology","authors":"Yang Hong, C. Chan, Jianping Guo, Y. Ng, Weiwei Shi, M. Ho, L. Leung, K. Leung, C. Choy, K. Pun","doi":"10.1109/EDSSC.2008.4760649","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760649","url":null,"abstract":"This paper presents a low-power, passive, EPCtrade C1G2-compatible UHF RFID tag design implemented in a 90 nm CMOS technology. In order to reduce its cost, diode-connected NMOSFETs in a standard CMOS technology is used instead of Schottky diodes. A sub-1 V, low temperature-coefficient voltage reference, using self-biased mutual compensation without large resistors, is proposed to save the chip area. To minimize the substantial leakage power in this technology, the baseband processor is designed with sufficient margins for subthreshold power supply. An energy-aware scheme is also implemented. Better power saving is achieved by using the RF envelope as clock and control signal of gating clock.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116227973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Power efficient charge pump circuit in standard twin-well CMOS technology","authors":"Jung-Chan Lee, Jin-Young Park, Yeonbae Chung","doi":"10.1109/EDSSC.2008.4760639","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760639","url":null,"abstract":"In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations shows that the proposed charge pump exhibits the higher output voltage, the larger output current, and thus a better power efficiency over the traditional twin-well charge pumps.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117209106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of contact positioning on the performance of stress induced MOSFETs","authors":"Xiangyu Zhang, Wei Wu, G. Du, R. Han, Xiaoyan Liu","doi":"10.1109/EDSSC.2008.4760696","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760696","url":null,"abstract":"In this paper, strain induced Si MOSFETs with multiple contact positioning strategies are simulated by ISE TCAD tool. The strain distribution of the MOSFETs with symmetric and asymmetric drain/source structure is investigated. The performance of the devices such as the Idsat and transfer characteristics is also simulated and compared. The results will help to model the characteristics of MOSFETs considering layout dependence.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121052622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seongjae Cho, I. Park, Jung Hoon Lee, J. Lee, Byung-Gook Park
{"title":"Program efficiency relying on channel conditions at NOR-type flash memory device based on silicon-on-insulator (SOI)","authors":"Seongjae Cho, I. Park, Jung Hoon Lee, J. Lee, Byung-Gook Park","doi":"10.1109/EDSSC.2008.4760667","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760667","url":null,"abstract":"Various types of flash memory devices are fabricated on silicon-on-insulator (SOI) substrate for efficient isolation and higher program efficiency nowadays. Since metal-oxide-semiconductor field effect transistors (MOSFETs) on SOI has a floating body and corresponding effects, it is quite difficult to predict the program efficiency of SOI-based NOR-type flash memory device making use of channel hot electron injection (CHEI) mechanism in program operation. The program efficiency is hard to control by back substrate bias unlike bulk silicon-based memory device, either. In this work, the dependence of program efficiency for SOI-based NOR-type flash memory device on channel conditions with regard to SOI thickness and channel doping concentration is thoroughly investigated by numerical simulation.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116912752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}