Design and challenges of passive UHF RFID tag in 90nm CMOS technology

Abstract

This paper presents a low-power, passive, EPCtrade C1G2-compatible UHF RFID tag design implemented in a 90 nm CMOS technology. In order to reduce its cost, diode-connected NMOSFETs in a standard CMOS technology is used instead of Schottky diodes. A sub-1 V, low temperature-coefficient voltage reference, using self-biased mutual compensation without large resistors, is proposed to save the chip area. To minimize the substantial leakage power in this technology, the baseband processor is designed with sufficient margins for subthreshold power supply. An energy-aware scheme is also implemented. Better power saving is achieved by using the RF envelope as clock and control signal of gating clock.