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A pseudo-flash ADC for large-channel-volume biomedical sensing applications 用于大通道体积生物医学传感应用的伪闪存ADC
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760722
C. Gong, Jyun-Wei Lu, Kai-Wen Yao, Jr-Yu Tsai, M. Shiue
{"title":"A pseudo-flash ADC for large-channel-volume biomedical sensing applications","authors":"C. Gong, Jyun-Wei Lu, Kai-Wen Yao, Jr-Yu Tsai, M. Shiue","doi":"10.1109/EDSSC.2008.4760722","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760722","url":null,"abstract":"This paper describes an ADC architecture termed pseudo-flash ADC and intended for biomedical sensing applications. It features high conversion speed which is the same as that of flash ADC, but has significantly lower hardware implementation overhead. Designed in a 0.18-mum standard CMOS technology in accordance with a specification of 250 KSamples/s and 6-bit resolution, the proposed ADC architecture consumes a total of nearly 290 muWunder the nominal supply voltage of 1.8 V, without the requirement of a large number of comparators as compared with the conventional flash ADC architecture.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114642696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Holistic methodology for designing ultra high-speed SHA-1 hashing cryptographic module in hardware 超高速SHA-1哈希加密模块硬件设计的整体方法
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760668
H. Michail, C. Goutis
{"title":"Holistic methodology for designing ultra high-speed SHA-1 hashing cryptographic module in hardware","authors":"H. Michail, C. Goutis","doi":"10.1109/EDSSC.2008.4760668","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760668","url":null,"abstract":"Nowadays security is a critical issue as long as electronic transactions are concerned. Moreover taking into consideration the rapid growth of e-commerce and the future needs, it is essential to achieve higher throughput rates for the incorporated security schemes. The most common components in such security schemes are a cipher block and a hash function, with the second one being hard to compete with the throughput achieved by cipher blocks. In this paper a top-down methodology is presented which manages to increase throughput of SHA-1 hash function hardware design about 160% comparing to conventional implementations with a minor area penalty.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121093722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Thermal modeling of enhancement LED package 增强型LED封装热建模
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760635
C. Weng
{"title":"Thermal modeling of enhancement LED package","authors":"C. Weng","doi":"10.1109/EDSSC.2008.4760635","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760635","url":null,"abstract":"Thermal management of LED packages consists of external cooling mechanisms, heat dissipaters, and thermal interfaces. While keeping cooling condition constant, junction temperature of LEDs with higher thermal resistance increases more rapidly, hence the luminous efficiency decreases more obviously. This paper includes the discussion about the calculation methods of the lightningpsilas heat transfer. Also the usage of the calculation method of heat resistances in equivalent electrical circuits, by which the difference between the temperature of the attention point inside the lighting and environment temperature can be directly obtained. Such a method is advanced on estimating the feasibility of a heat transferpsilas structure. The calculation process has been demonstrated by an example of cooling of LEDs lighting in this paper. In particular, the operation package heat transfer enhancement is required by most package manufacturers with a decrease of 20%-30% of the thermal resistance over conventional package geometries. More specifically, the present invention and study relate to a LEDs package with heat dissipation enhancements.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122115500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.9V 2.7µW small-area 100µs+ analog CMOS tunable-delay circuit utilizing Miller effect 一种利用米勒效应的0.9V 2.7µW小面积100µs+模拟CMOS可调延迟电路
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760685
D. Ng, N. Wong, D. Kwong
{"title":"A 0.9V 2.7µW small-area 100µs+ analog CMOS tunable-delay circuit utilizing Miller effect","authors":"D. Ng, N. Wong, D. Kwong","doi":"10.1109/EDSSC.2008.4760685","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760685","url":null,"abstract":"We report a novel analog delay circuit based on Miller effect that features small die area and tunable delay in the order of 100 mus, without using any external component. The delay time can be tuned by varying the biasing current, capacitor sizes, transconductance of the gain-stage transistor and the corresponding output impedances. The turn-on threshold of the delay circuit can also be raised, as required in some applications, by utilizing the body effect of the input transistors. The circuit has a very low startup voltage (ap0.9 V) and consumes a very low power (ap2.7 muW) in a standard 1 mum pure CMOS process with Vtn ap 0.65 V and Vtp ap 0.8 V at 25degC. Circuit operations are elaborated and its function is verified by simulation and silicon measurement.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123192023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Pentacene thin-film transistors with HfO2 gate dielectric annealed in NH3 or N2O 在NH3或N2O中退火的HfO2栅极介质并五苯薄膜晶体管
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760740
L. Deng, W. Tang, C. Leung, P. Lai, J. Xu, C. Che
{"title":"Pentacene thin-film transistors with HfO2 gate dielectric annealed in NH3 or N2O","authors":"L. Deng, W. Tang, C. Leung, P. Lai, J. Xu, C. Che","doi":"10.1109/EDSSC.2008.4760740","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760740","url":null,"abstract":"Pentacene-based organic thin-film transistor (OTFT) with HfO<sub>2</sub> as gate dielectric is studied in this work. The HfO<sub>2</sub> dielectric was prepared by RF sputtering at room temperature, and subsequently annealed in N<sub>2</sub>O or NH<sub>3</sub> at 200degC. The OTFTs were characterized by IV measurement and 1/f noise measurement. The OTFTs show small threshold voltage and can operate at as low as 3 V. Results indicate that the OTFT annealed in NH<sub>3</sub> shows higher carrier mobility, larger on/off current ratio, smaller sub-threshold swing and smaller Hooge parameter than the OTFT annealed in N<sub>2</sub>O. Therefore, NH<sub>3</sub>-annealed HfO<sub>2</sub> is a promising gate dielectric for the fabrication of high-performance OTFTs.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116472473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Modeling of dynamic threshold voltage in high K gate stack and the application in FinFET reliability 高K栅极堆叠动态阈值电压建模及其在FinFET可靠性中的应用
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760661
Chenyue Ma, Bo Li, Lining Zhang, Jin He, Xing Zhang, Xinnan Lin
{"title":"Modeling of dynamic threshold voltage in high K gate stack and the application in FinFET reliability","authors":"Chenyue Ma, Bo Li, Lining Zhang, Jin He, Xing Zhang, Xinnan Lin","doi":"10.1109/EDSSC.2008.4760661","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760661","url":null,"abstract":"A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (Id) degradation in FinFET is much more obvious than normal MOSFETs with the same processes and the variation of Id is slower in higher temperature. However, the dynamic threshold voltage in high K stack seems not affect the delay time of reverser simulated by HSPICE.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124507551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ESD device simulation in a pre-Si phase 在预si相位ESD器件仿真
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760700
Zhiguo Li, S. Yue
{"title":"ESD device simulation in a pre-Si phase","authors":"Zhiguo Li, S. Yue","doi":"10.1109/EDSSC.2008.4760700","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760700","url":null,"abstract":"In this paper, a novel approach that performs device simulation in the pre-Si phase to evaluate the robustness of the ESD protection device is presented. Several key parameters, such as the spacing from gate to source contact, the spacing from gate to drain contact, the length of the gate and the width of the gate are researched using the simulator MEDICI. Tunneling phenomenon is also observed and expatiated in ESD protection device. An empirical equation is derived based on the simulation to calculate the failure threshold of the device. The prediction of ESD protection circuit performance in early design phase shortens the design cycle and reduces the cost.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127599599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparison of top and bottom-contact organic thin film transistors for analog circuit applications 模拟电路中顶触和底触有机薄膜晶体管的比较
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760672
M. N. Islam, B. Mazhari
{"title":"Comparison of top and bottom-contact organic thin film transistors for analog circuit applications","authors":"M. N. Islam, B. Mazhari","doi":"10.1109/EDSSC.2008.4760672","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760672","url":null,"abstract":"A comparative analysis of top and bottom-contact organic thin film transistors (OTFTs) for analog circuit applications is presented using a common source amplifier as an example. Using 2D numerical device simulations, it is shown that significantly higher product of voltage gain and 3dB bandwidth can be obtained using a top-contact OTFT. This advantage results primarily from a smaller gate-drain capacitance and increases in amplifiers designed for higher voltage gain.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Modeling current transport in carbon nanotube transistors 碳纳米管晶体管电流输运模型
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760743
M. Pourfath, S. Selberherr
{"title":"Modeling current transport in carbon nanotube transistors","authors":"M. Pourfath, S. Selberherr","doi":"10.1109/EDSSC.2008.4760743","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760743","url":null,"abstract":"Carbon nanotubes (CNTs) have been studied in recent years due to their exceptional electronic, opto-electronic, and mechanical properties. To explore the physics of carbon nanotube field-effect transistors (CNT-FETs) self-consistent quantum mechanical simulations have been performed. Both the electron-photon and electron-phonon interactions in CNT-FETs have been analyzed numerically, employing the non-equilibrium Greenpsilas function formalism. The numerical challenges for the analysis of carbon nanotube based photo-detectors have been investigated. The results indicate the non-locality of electron-photon interaction. For accurate analysis it is essential to include many off-diagonals of the electron-photon self-energy. Electron-phonon interaction parameters, such as electron-phonon coupling strength and phonon energy, strongly depend on the chirality and the diameter of the carbon nanotube. The steady-state and the dynamic response of carbon nanotube based transistors have been studied for a wide range of electron-phonon interaction parameters.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"133 32","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131745546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A numerical simulation study of a nanoscaled side selective buried oxide MOSFET 纳米级侧选择性埋地氧化MOSFET的数值模拟研究
2008 IEEE International Conference on Electron Devices and Solid-State Circuits Pub Date : 2008-12-01 DOI: 10.1109/EDSSC.2008.4760640
S. Loan, S. Qureshi, S. S. Kumar Iyer
{"title":"A numerical simulation study of a nanoscaled side selective buried oxide MOSFET","authors":"S. Loan, S. Qureshi, S. S. Kumar Iyer","doi":"10.1109/EDSSC.2008.4760640","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760640","url":null,"abstract":"Two dimensional numerical simulation of nanoscaled selective buried oxide (SELBOX) based MOSFET is performed. In this device an opening is provided under the device channel in the buried oxide (BOX). A comparative analysis of the SELBOX, bulk and SOI (Silicon-on-Insulator) devices for various performance measuring parameters has been done. The simulation study has revealed that by properly choosing various device parameters, the overall performance of the SELBOX device is found to be optimal to that of the conventional MOSFET and SOI device, particularly when self heating, short channel effects and breakdown voltage are considered together.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127867292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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