{"title":"Cascaded classification for hardware face detection","authors":"I. Zheng, Xiaoxiao Zhang, F. Flitti, A. Bermak","doi":"10.1109/EDSSC.2008.4760695","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760695","url":null,"abstract":"This paper presents a face detection hardware architecture which is based on a newly proposed algorithm using cascaded classifiers with vector angle similarity measurement between the investigated image and the face/non-face centroids. The proposed system is composed of three major modules: Best fit plane removal unit, Histogram equalization unit, and cascaded classification unit. Comprehensive optimization at both the algorithmic and hardware levels has enabled performance improvement and area reduction. The vector angle similarity measure-based algorithm is employed to achieve acceptable classification accuracy and high-speed. The cascaded classification architecture is designed in a parallel mode to achieve low latency and low iteration time. The overall system was designed in VHDL and synthesized and implemented using Xilinx FPGA vertex4 family board. Experimental results on real-time captured face images prove the system reliability and achievement of real-time classification performance which is comparable to a software implementation while running at a frame rate of 63 frames per second at an image resolution of 64times64 pixels. The proposed architecture is scalable and can be extended to higher resolution.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133843937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhanced performance of Si MOS capacitors with HfTaOxNy gate dielectric by using AlOxNy or TaOxNy interlayer","authors":"C.X. Li, X.F. Zhang, J. Xu, P. Lai","doi":"10.1109/EDSSC.2008.4760738","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760738","url":null,"abstract":"Si MOS capacitors with HfTa oxide and oxynitride as gate dielectric were fabricated. Moreover, AlO<sub>x</sub>N<sub>y</sub> or TaO<sub>x</sub>N<sub>y</sub> was used as the interlayer between HfTa oxynitride and Si substrate to improve the electrical quality of the capacitors. Experimental results showed that the HfTaO<sub>x</sub>N<sub>y</sub> capacitor with TaO<sub>x</sub>N<sub>y</sub> interlayer achieved better performance with larger capacitance and smaller leakage current than its counterpart with AlO<sub>x</sub>N<sub>y</sub> interlayer.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122088767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Statistical modeling of layout-dependent characteristic fluctuations for multi-finger MOSFETs","authors":"Chulhyun Park, J. Kang, Seong-ook Jung, Ilgu","doi":"10.1109/EDSSC.2008.4760677","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760677","url":null,"abstract":"Large-signal models using extracted parasitic resistance are proposed for multi-finger MOSFETs and the statistical variations of parasitic resistances are investigated using statistical modeling. The extracted model parameters for the proposed models are verified with measured data. The models can explain the large-signal characteristics of multi-finger MOSFETs. Using the equivalent circuit model, the characteristic variations are statistically modeled with varying the gate layout factors and the extracted parasitic resistances. Based on the results, the gate geometry and extracted parasitic resistances. which are closely related to the source bias, can impact on the characteristic fluctuations of multi-finger MOSFETs.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125966331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cross-sectional shape effects on the electronic properties of Silicon nanowires","authors":"R. Sajjad, S. Bhowmick, Q. Khosru","doi":"10.1109/EDSSC.2008.4760704","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760704","url":null,"abstract":"The electronic properties of Silicon nanowires are studied using empirical tight binding sp3d5s* model for three different cross-sectional shapes - square, circular and triangular. For two different growth directions <100> and <110>, it is observed that the electron effective masses at the Gamma point is lowest for triangular wire. The conduction band valley splitting at the Gamma point for <100> wire is higher for triangular wire compared to the other two shapes. The valence bands are more degenerate for circular wire than the other two and their splitting is highest for square wire. Hole effective mass at the valence band maxima for <100> wire is significantly lower for triangular wire than that of the other two shapes which show large increase in hole effective mass as a result of quantum confinement. These electronic properties are compared against same cross-section area which is varied from 0-30 nm2. The energy band gap shows no variation due to wire shape. It only depends on cross-section area. Variations in the electronic properties due to shape diminish gradually as cross-sectional area is increased.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129417802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new two-dimensional analytical model for short-channel Tri-material gate-stack SOI MOSFET’s","authors":"T. Chiang","doi":"10.1109/EDSSC.2008.4760750","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760750","url":null,"abstract":"Based on the exact solution of the two-dimensional Poisson equation, a new analytical behavior model consisting of the two-dimensional potential and threshold voltage for the short-channel tri-material gate-stack SOI MOSFETpsilas is developed. The model is verified by its good agreement with the numerical simulation of the device simulator MEDICI. The model not only offers physical insight into the device physics but also provides guidance for the basic design of the device.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127046772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu Chen, Jin He, Xuehao Mu, H. Lou, Lining Zhang, Yan Song
{"title":"Terahert detection analysis of nanowire gated field effect transistor","authors":"Yu Chen, Jin He, Xuehao Mu, H. Lou, Lining Zhang, Yan Song","doi":"10.1109/EDSSC.2008.4760659","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760659","url":null,"abstract":"An analytical terahertz (THz) detection model of the Silicon nanowire MOSFET (NWFET) is developed in this paper. Beginning from the fundamental hydrodynamic transport equations, the expressions of the velocity spatial distribution and inversion charge transport are obtained. Under the reasonable boundary, an analytical model of the photoresponse of the NWFET is derived out. The comparison between analytical calculation and numerical results confirmed the proposed model. Moreover, the plasma wave transport behavior in the NWFET is analyzed in detail from the presented model and some significant characteristics are demonstrated.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132067188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high reliability CMOS implantable interface for wireless neural recording microsystem","authors":"Hongge Li, Youguang Zhang","doi":"10.1109/EDSSC.2008.4760664","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760664","url":null,"abstract":"A novel wireless implantable microsystem using a high-reliability digital technology is proposed for recording the hybrid neural signal. In order to enhance the neural recording intactness, we employ a kind of high-reliability design architecture, which includes a self-check circuit and a transmitter channel error check circuit. The proposed high-reliability structure can identify possible faults in any implantable interface. A dynamical pattern double channel circuit is designed for the signal synchronous transfer in this interface. A low-power self-check circuit is designed too. The high-reliability and low-power implantable interface using a full-CMOS technology has been designed and verified. A prototype has been implemented, whose correct operation has been verified by mean of post-layout simulations and experimental measurements.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114226204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High frequency low cost CMOS LNA design procedure for the wireless industry","authors":"A. Ahmed, J. Wight","doi":"10.1109/EDSSC.2008.4760669","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760669","url":null,"abstract":"This paper presents a design procedure used in industry for designing low-power narrowband high-gain CMOS LNAs for wireless applications for frequencies greater than 6 GHz, with considerations for process variations. This paper does not give detailed derivations of equations. Rather, it gives the simulation procedure and methodology that converges quickly to a practical optimized solution for LNA designs mostly used in mobile communication industry for mass-production, requiring minimal time and resources from the designer. It takes a wholistic design approach where all factors, including manufacturing costs, technology choice and applications are considered. It explains how to design the appropriate topology from the ldquogrounds uprdquo approach, and then giving the designer the option to match the ports or not, depending on if it is appropriate. This method yields these LNA parameters at 6.5 GHz: S21=18 dB, NFmin=3.22 dB, NF=6.1 dB and S22,<-15 dB with only 6.4 mW (plus 2.5 mW for narrowband output match) power consumption over 1.2 V supply.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121116890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low-leakage and low-power implementation of high-speed 65nm logic gates","authors":"Tsung-Yi Wu, L. Lu, Cheng-Hsun Liang","doi":"10.1109/EDSSC.2008.4760641","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760641","url":null,"abstract":"In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. Logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 35.0% and 20.0%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121720756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-clamping thyristor mode LIGBT based on SOI","authors":"G. Xie, Bo Zhang","doi":"10.1109/EDSSC.2008.4760675","DOIUrl":"https://doi.org/10.1109/EDSSC.2008.4760675","url":null,"abstract":"A new structure of SOI-LIGBT operated at thyristor mode with unique self-clamping character (TM-SOI LIGBT) integrated in SPICs has been studied and analyzed. We used 15 mum SOI layer and 3 mum SiO4, respectively to obtain a breakdown voltage exceeding 500 V. Comparison of not only a trade off between forward voltage drop and turn off loss but also a forward biased safe operating area (FBSOA) with conventional LIGBT based on SOI has been investigated. 2D Mix-mode numerical analysis using MEDICI shows that the proposed structure dramatically reduced the forward saturation voltage drop to about 21.3%, and turn off time 20%, with large FBSOA and has better current density when at on state and controllable current capability when at off state.","PeriodicalId":234055,"journal":{"name":"2008 IEEE International Conference on Electron Devices and Solid-State Circuits","volume":"55 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114043155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}