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2013 International Symposium on Rapid System Prototyping (RSP)最新文献

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Enforcing software engineering tools interoperability: An example with AADL subsets 加强软件工程工具的互操作性:AADL子集的示例
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683959
V. Gaudel, Frank Singhoff, A. Plantec, J. Hugues, P. Dissaux, J. Legrand
{"title":"Enforcing software engineering tools interoperability: An example with AADL subsets","authors":"V. Gaudel, Frank Singhoff, A. Plantec, J. Hugues, P. Dissaux, J. Legrand","doi":"10.1109/RSP.2013.6683959","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683959","url":null,"abstract":"Model-Based Engineering is now a valuable asset to design complex real-time systems. Toolchains are assembled to cover the various stages of the process: high-level modeling, analysis and code generation. Yet tools put heterogeneous requirements on models: specific modeling patterns must be respected so that a given analysis is performed. This creates an interoperability paradox: models must be tuned not given system requirements, but to abide to tools capabilities. In this paper, we propose a systematic process to define the definition, comparison and enforcement of tools-specific subsets. Thus, we guide the user in selecting the tools that could support its engineering process. Our contribution is illustrated in the context of the AADL Architecture Design Language.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116114462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs 一种设计部分可重构mpsoc的启发式方法
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683965
Riccardo Cattaneo, C. Pilato, Gianluca Durelli, M. Santambrogio, D. Sciuto
{"title":"SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs","authors":"Riccardo Cattaneo, C. Pilato, Gianluca Durelli, M. Santambrogio, D. Sciuto","doi":"10.1109/RSP.2013.6683965","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683965","url":null,"abstract":"The exploitation of the capabilities offered by reconfigurable architectures is traditionally a demanding task due to the intrinsic time consuming and error prone customization of these systems around the specific application. Moreover, existing approaches are not able to integrate the notion of partial and dynamic reconfiguration (PDR) from the early stages of the decision phases, potentially leading to sub-optimal solutions. In this work, we propose SMASH (Simultaneous Mapping and Scheduling with Heuristics), a highly automated design methodology focused on explicitly taking into account PDR during the design of reconfigurable designs. It combines heuristics for both the design of the architecture and the mapping and scheduling of the partitioned application. We show how this additional degree of freedom leads to architectures whose performance are improved with respect to the baseline.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Customizable RTOS to support communication infrastructures and to improve design space exploration in MPSoCs 可定制的RTOS支持通信基础设施，并改进mpsoc中的设计空间探索
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683969
A. Aguiar, S. J. Filho, F. Magalhães, Fabiano Hessel
{"title":"Customizable RTOS to support communication infrastructures and to improve design space exploration in MPSoCs","authors":"A. Aguiar, S. J. Filho, F. Magalhães, Fabiano Hessel","doi":"10.1109/RSP.2013.6683969","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683969","url":null,"abstract":"Multiprocessed System-on-Chip (MPSoCs) have become a recurrent implementation alternative to modern embedded systems and, lately, have counted on resources previously available only on general purpose machines. In this context, it is possible to highlight that many techniques formerly adopted in general-purpose computers have been studied and adapted to the embedded reality. Thus, embedded communication infrastructures such as buses and networks-on-Chip (NoCs) are based on general-purpose solutions and are widely accepted for embedded systems. Also, embedded systems make use of Operating Systems (OS), as they provide standard interfaces to access hardware resources, including the communication facilities. However, although the underlying communication infrastructure can differ in order to improve a given metric, such as performance, power or area, it is desirable that the software layer remains the same, especially in terms of the application's and OS's code improving the overall software quality. Still, certain OS parameters can directly influence on the overall system performance. This paper presents a highly configurable Real Time OS (RTOS) that implements a communication protocol to provide a transparent communication interface for both bus- and NoC-based MPSoCs' applications.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132811028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A framework for instruction encoding designs on embedded processors 嵌入式处理器指令编码设计框架
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683967
R. Santos, Renan Marks, Renato Santos
{"title":"A framework for instruction encoding designs on embedded processors","authors":"R. Santos, Renan Marks, Renato Santos","doi":"10.1109/RSP.2013.6683967","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683967","url":null,"abstract":"This work presents a software framework implementing a unified infrastructure for instruction encoding techniques on embedded processors. The proposed framework has been used together with the Pattern Based Instruction Word (PBIW) technique to encodeprograms from the VEX and SPARC instruction sets. Given the common complexity around the design of an instruction encoding algorithm, our proposed software framework is a viable alternative for speeding up this task. The experiments show that the framework makes it able to match the PBIW encoding technique to different ISAs and target machines. Our experiments show a compression ratio up to 54.82% for SPARC programs and up to 59.56% for VEX programs using the PBIW encoding algorithm and the framework. Our experiments also show that some encoded SPARC programs have a performance speedup of 67% compared to non-encoded SPARC programs.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128429813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
BaBaNoC: An asynchronous network-on-chip described in Balsa BaBaNoC:用Balsa描述的一种异步片上网络
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683956
Matheus T. Moreira, F. Magalhães, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans
{"title":"BaBaNoC: An asynchronous network-on-chip described in Balsa","authors":"Matheus T. Moreira, F. Magalhães, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans","doi":"10.1109/RSP.2013.6683956","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683956","url":null,"abstract":"The downscaling of silicon technology and the possibility of building MPSoCs, make intrachip communication a mainstream research topic. NoCs are an elegant solution to provide communication scalability and modularity. NoCs are already common in MPSoC design. Moreover, new technology challenges point to a growth in the use of non-synchronous NoCs. However, the design of asynchronous infrastructures with current EDA tools is challenging. That is due to the fact that most of these tools are oriented towards synchronous design. This work proposes and evaluates a fully asynchronous NoC router based on the Balsa language and framework. The design is validates through FPGA synthesis.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115838095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Visual exploration of changing FPGA architectures in the VTR project 可视化探索改变FPGA架构在VTR项目
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683953
K. Nasartschuk, R. Herpers, K. Kent
{"title":"Visual exploration of changing FPGA architectures in the VTR project","authors":"K. Nasartschuk, R. Herpers, K. Kent","doi":"10.1109/RSP.2013.6683953","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683953","url":null,"abstract":"Developing applications for Field Programmable Gate Array (FPGA) devices utilizes Computer Aided Design (CAD) flows. The transition from a high level Verilog hardware description to the optimized structure of programmed soft logic blocks and routing structure includes stages such as Verilog synthesis, hardware mapping, logical synthesis, packing, placement and routing. The VTR CAD flow is a collaborative project consisting of Odin II (University of New Brunswick), ABC (University of California, Berkeley) and VPR (University of Toronto), which offers an FPGA CAD flow for research and experimentation purposes. This paper describes developments in the visualization and simulation modules of Odin II, the first stage of the CAD flow. The contributions include new netlist visualization possibilities as well as an extended netlist simulator capable of simulating circuits with multiple clocks and providing extended generic structure simulation abilities. This results in the possibility to explore and simulate a larger set of new FPGA architectures and evaluate them using the VTR flow.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124529914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Seamless integration of HW/SW components in a HLS-based SoC design environment 在基于hls的SoC设计环境中无缝集成硬件/软件组件
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683966
T. Mück, A. A. Fröhlich
{"title":"Seamless integration of HW/SW components in a HLS-based SoC design environment","authors":"T. Mück, A. A. Fröhlich","doi":"10.1109/RSP.2013.6683966","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683966","url":null,"abstract":"With system-on-chip (SoC) designs growing in complexity, system-level approaches that leverage on high-level synthesis (HLS) techniques are becoming the workhorse of current SoC design flows. In this scenario, we propose a component communication framework that allows for the seamless integration of hardware and software components in a HLS-capable environment. The proposed infrastructure relies on C++ static metaprogramming techniques to efficiently abstract communication details in high-level C++ implementations of components. We show how these mechanisms can be integrated with virtual platforms at different levels of abstraction, resulting in a design flow that enables the rapid design space exploration of SoC designs.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133622652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Routing algorithm for multi-FPGA based systems using multi-point physical tracks 基于多点物理轨迹的多fpga系统的路由算法
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683951
Qingshan Tang, M. Tuna, H. Mehrez
{"title":"Routing algorithm for multi-FPGA based systems using multi-point physical tracks","authors":"Qingshan Tang, M. Tuna, H. Mehrez","doi":"10.1109/RSP.2013.6683951","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683951","url":null,"abstract":"Multi-FPGA boards suffer from large timing delays in inter-FPGA physical tracks compared to intra-FPGA track delays, as well as a limited bandwidth between FPGAs due to the limited number of I/Os per FPGA. In order to tackle this problem, an algorithm which routes multi-terminal nets in multi-point tracks is proposed in this paper to spare FPGA I/Os. Experiments are conducted using Gaisler Research Benchmarks. Firstly, each testbench will be implemented in an off-the-shelf board. The results show that the system frequency can be increased in the off-the-shelf board by the proposed routing algorithm. Secondly, an automatic design flow which generates a custom multi-FPGA board is enhanced by generating multi-point tracks in the board, and each testbench will be implemented with the proposed routing algorithm in custom boards. The results show that the system frequency is improved in the custom board with both 2- and multi-point tracks.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133891617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
FPGA-based HPC application design for non-experts 基于fpga的非专家HPC应用设计
2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-02-11 DOI: 10.1145/2435264.2435334
David Uliana, Krzysztof Kepa, P. Athanas
{"title":"FPGA-based HPC application design for non-experts","authors":"David Uliana, Krzysztof Kepa, P. Athanas","doi":"10.1145/2435264.2435334","DOIUrl":"https://doi.org/10.1145/2435264.2435334","url":null,"abstract":"In the current era of big-data computing, most non-engineer domain experts lack the skills needed to design FPGA-based hardware accelerators to address big-data problems in their fields. This work presents bFlow, a development environment that facilitates the assembly of such accelerators, specifically those targeting FPGA-based hybrid computing platforms, such as the Convey HC series. This framework attempts to address the above problem by making use of an abstracted, graphical front-end more friendly to users without computer engineering backgrounds than traditional, HDL-based design environments, as well as by accelerating bitstream compilation by means of incremental implementation techniques. bFlow's performance, usability, and application to big-data life-science problems were tested by participants of an NSF-funded Summer Institute organized by the Virginia Bioinformatics Institute (VBI). In about one week, a group of four non-engineering participants made significant improvements to a reference Smith-Waterman implementation, adding functionality and scaling theoretical throughput by a factor of 32.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131628212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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