{"title":"在基于hls的SoC设计环境中无缝集成硬件/软件组件","authors":"T. Mück, A. A. Fröhlich","doi":"10.1109/RSP.2013.6683966","DOIUrl":null,"url":null,"abstract":"With system-on-chip (SoC) designs growing in complexity, system-level approaches that leverage on high-level synthesis (HLS) techniques are becoming the workhorse of current SoC design flows. In this scenario, we propose a component communication framework that allows for the seamless integration of hardware and software components in a HLS-capable environment. The proposed infrastructure relies on C++ static metaprogramming techniques to efficiently abstract communication details in high-level C++ implementations of components. We show how these mechanisms can be integrated with virtual platforms at different levels of abstraction, resulting in a design flow that enables the rapid design space exploration of SoC designs.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Seamless integration of HW/SW components in a HLS-based SoC design environment\",\"authors\":\"T. Mück, A. A. Fröhlich\",\"doi\":\"10.1109/RSP.2013.6683966\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With system-on-chip (SoC) designs growing in complexity, system-level approaches that leverage on high-level synthesis (HLS) techniques are becoming the workhorse of current SoC design flows. In this scenario, we propose a component communication framework that allows for the seamless integration of hardware and software components in a HLS-capable environment. The proposed infrastructure relies on C++ static metaprogramming techniques to efficiently abstract communication details in high-level C++ implementations of components. We show how these mechanisms can be integrated with virtual platforms at different levels of abstraction, resulting in a design flow that enables the rapid design space exploration of SoC designs.\",\"PeriodicalId\":227927,\"journal\":{\"name\":\"2013 International Symposium on Rapid System Prototyping (RSP)\",\"volume\":\"257 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 International Symposium on Rapid System Prototyping (RSP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RSP.2013.6683966\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 International Symposium on Rapid System Prototyping (RSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RSP.2013.6683966","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Seamless integration of HW/SW components in a HLS-based SoC design environment
With system-on-chip (SoC) designs growing in complexity, system-level approaches that leverage on high-level synthesis (HLS) techniques are becoming the workhorse of current SoC design flows. In this scenario, we propose a component communication framework that allows for the seamless integration of hardware and software components in a HLS-capable environment. The proposed infrastructure relies on C++ static metaprogramming techniques to efficiently abstract communication details in high-level C++ implementations of components. We show how these mechanisms can be integrated with virtual platforms at different levels of abstraction, resulting in a design flow that enables the rapid design space exploration of SoC designs.