2013 International Symposium on Rapid System Prototyping (RSP)最新文献

An implementation of a distributed fault-tolerant mechanism for 2D mesh NoCs 二维网格noc分布式容错机制的实现

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683954

C. Marcon, Alexandre M. Amory, F. T. Bortolon, T. Webber, Thomas Volpato, Jader Munareto

引用次数: 0

Quota setting router architecture for quality of service in GALS NoC GALS NoC中服务质量的配额设置路由器架构

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683957

Kazem Cheshmi, M. Soltaniyeh, S. Mohammadi, Jelena Trajkovic

引用次数: 9

Emulation-based design evaluation of reader/smart card systems 基于仿真的读卡器/智能卡系统设计评价

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683962

N. Druml, M. Menghin, Daniel Kroisleitner, C. Steger, R. Weiss, H. Bock, J. Haid

{"title":"Emulation-based design evaluation of reader/smart card systems","authors":"N. Druml, M. Menghin, Daniel Kroisleitner, C. Steger, R. Weiss, H. Bock, J. Haid","doi":"10.1109/RSP.2013.6683962","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683962","url":null,"abstract":"Design exploration and evaluation are essential tasks during a product's development cycle. Simulation and hardware emulation are common techniques to explore and evaluate the functionality of hardware/software designs. However, when it comes to distributed secure applications, like contactless reader/smart card systems, non-functional design properties and system aspects (e.g., conctactless power transfer, power consumption) have to be regarded too. State-of-the-art simulation-based and emulation-based design exploration tools cover these design issues and system aspects only to some extent. Here we present a design exploration framework for complete reader/smart card systems using state-of-the-art model-based emulation and estimation techniques. This novel system-based approach is of high importance because of the high availability of battery powered mobile readers (i.e. smart phones) and novel mobile application fields. Contactless power transfer and power consumption analyses of reader and smart cards can be performed for each clock cycle and in real time. Thus, novel system-level power and security optimization techniques can be evaluated considering the reader/smart card system as a whole. We demonstrate the application of our exploration framework by means of a typical Diffie-Hellman key exchange between reader and smart card and highlight power optimization possibilities.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114766956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs YAPPA:基于编译器的并行化框架，用于mpsoc上的不规则应用程序

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683968

S. Lovergine, Antonino Tumeo, Oreste Villa, Fabrizio Ferrandi

{"title":"YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs","authors":"S. Lovergine, Antonino Tumeo, Oreste Villa, Fabrizio Ferrandi","doi":"10.1109/RSP.2013.6683968","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683968","url":null,"abstract":"Modern embedded systems include hundreds of cores. Because of the difficulty in providing a fast, coherent memory architecture, these systems usually rely on noncoherent, non-uniform memory architectures with private memories for each core. However, programming these systems poses significant challenges. The developer must extract large amounts of parallelism, while orchestrating communication among cores to optimize application performance. These issues become even more significant with irregular applications, which present data sets difficult to partition, unpredictable memory accesses, unbalanced control flow and fine grained communication. Hand-optimizing every single aspect is hard and time-consuming, and it often does not lead to the expected performance. There is a growing gap between such complex and highly-parallel architectures and the high level languages used to describe the specification, which were designed for simpler systems and do not consider these new issues. In this paper we introduce YAPPA (Yet Another Parallel Programming Approach), a compilation framework for the automatic parallelization of irregular applications on modern MPSoCs based on LLVM. We start by considering an efficient parallel programming approach for irregular applications on distributed memory systems. We then propose a set of transformations that can reduce the development and optimization effort. The results of our initial prototype confirm the correctness of the proposed approach.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127361338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Rapid safety evaluation of hardware architectural designs compliant with ISO 26262 符合ISO 26262的硬件架构设计的快速安全评估

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683960

N. Adler, S. Otten, Markus Mohrhard, K. Müller-Glaser

引用次数: 9

Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes QC-LDPC码可重构解码器架构的快速设计与原型设计

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683963

Purushotham Murugappa, Vianney Lapôtre, A. Baghdadi, M. Jézéquel

引用次数: 5

MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs MAMPSx:快速合成可预测异构mpsoc的设计框架

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683970

Shakith Fernando, Firew Siyoum, Yifan He, Akash Kumar, H. Corporaal

{"title":"MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs","authors":"Shakith Fernando, Firew Siyoum, Yifan He, Akash Kumar, H. Corporaal","doi":"10.1109/RSP.2013.6683970","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683970","url":null,"abstract":"Heterogeneous Multiprocessor System-on-Chips (HMPSoC) are becoming popular as a means of meeting energy efficiency requirements of modern embedded systems. However, as these HMPSoCs run multimedia applications as well, they also need to meet real-time requirements. Designing these predictable HMPSoCs is a key challenge, as the current design methods for these platforms are either semi-automated, non-predictable, or have limited heterogeneity. In this paper, we propose a design framework to generate and program HMPSoC designs in a rapid and predictable manner. It takes the application specifications and the architecture model as input and generates the entire HMPSoC, for FPGA prototyping, that meets the throughput constraints. The experimental results show that our framework can provide a conservative bound on the worst-case throughput of the FPGA implementation. We also present results of a case study that computes the area-power trade-offs of an industrial vision application. The entire design space exploration of all configurations was completed in 8 hours. A tool-chain targeting the Xilinx Zynq FPGA is also presented.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"77 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123270953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

FlexOE: A congestion-aware routing algorithm for NoCs FlexOE:用于noc的拥塞感知路由算法

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683958

O. A. D. L. Junior, V. Fresse, F. Rousseau

引用次数: 3

Performance modeling for designing NoC-based multiprocessors 基于noc的多处理器设计的性能建模

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683955

Takashi Nakada, Shinobu Miwa, K. Yano, Hiroshi Nakamura

{"title":"Performance modeling for designing NoC-based multiprocessors","authors":"Takashi Nakada, Shinobu Miwa, K. Yano, Hiroshi Nakamura","doi":"10.1109/RSP.2013.6683955","DOIUrl":"https://doi.org/10.1109/RSP.2013.6683955","url":null,"abstract":"Network-on-Chip (NoC) based multiprocessors have become popular as a scalable alternative to classical bus architectures. The performance evaluation of NoC-based multiprocessors is largely based on simulation. However, precise simulation is extremely slow. Additionally, there are many design parameters that affect the total performance. Therefore, it is practically impossible to use the precise simulation for the design space exploration purposes. To alleviate this problem, prototyping NoC systems and estimating their performances are critically important. In this paper, we present a generalized novel performance model that combined with the simulations for designing NoC-based multiprocessors. We revealed that the performance impact of cache and network latencies are dominant. Moreover, network congestion rarely happens under near appropriate configuration. Thus, the performance model is mainly constructed using the hardware parameters and the statistics that obtained from a simple cache simulation that is separated from the network behavior. The proposed performance model is used not only to obtain fast and accurate performance, but also to guide the NoC-based multiprocessor design space exploration. The accuracy of our approach and its practical use are illustrated through simulation. The results showed that proposed model can estimate performance with only 3.4% error on average and 21% at worst. We also confirmed that our evaluation framework can estimate 360 times faster than the brute force full system simulation.","PeriodicalId":227927,"journal":{"name":"2013 International Symposium on Rapid System Prototyping (RSP)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132739199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A flexible framework for modeling and simulation of multipurpose wireless networks 一种灵活的多用途无线网络建模与仿真框架

2013 International Symposium on Rapid System Prototyping (RSP) Pub Date : 2013-12-16 DOI: 10.1109/RSP.2013.6683964

Vinicius Bohrer, Ramon Fernandes, C. Marcon, T. Webber, L. Poehls, R. Czekster, Fabiano Hessel

引用次数: 4