A framework for instruction encoding designs on embedded processors

Abstract

This work presents a software framework implementing a unified infrastructure for instruction encoding techniques on embedded processors. The proposed framework has been used together with the Pattern Based Instruction Word (PBIW) technique to encodeprograms from the VEX and SPARC instruction sets. Given the common complexity around the design of an instruction encoding algorithm, our proposed software framework is a viable alternative for speeding up this task. The experiments show that the framework makes it able to match the PBIW encoding technique to different ISAs and target machines. Our experiments show a compression ratio up to 54.82% for SPARC programs and up to 59.56% for VEX programs using the PBIW encoding algorithm and the framework. Our experiments also show that some encoded SPARC programs have a performance speedup of 67% compared to non-encoded SPARC programs.