FPGA-based HPC application design for non-experts

Abstract

In the current era of big-data computing, most non-engineer domain experts lack the skills needed to design FPGA-based hardware accelerators to address big-data problems in their fields. This work presents bFlow, a development environment that facilitates the assembly of such accelerators, specifically those targeting FPGA-based hybrid computing platforms, such as the Convey HC series. This framework attempts to address the above problem by making use of an abstracted, graphical front-end more friendly to users without computer engineering backgrounds than traditional, HDL-based design environments, as well as by accelerating bitstream compilation by means of incremental implementation techniques. bFlow's performance, usability, and application to big-data life-science problems were tested by participants of an NSF-funded Summer Institute organized by the Virginia Bioinformatics Institute (VBI). In about one week, a group of four non-engineering participants made significant improvements to a reference Smith-Waterman implementation, adding functionality and scaling theoretical throughput by a factor of 32.