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2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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A Critical View of IGBT Buffer Designs for 200 °C Operation 200°C操作下IGBT缓冲设计的关键观点
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757638
E. Buitrago, A. Mesemanolis, M. Andenna, C. Papadopoulos, C. Corvasce, J. Vobecký, Munaf T. A. Rahimo
{"title":"A Critical View of IGBT Buffer Designs for 200 °C Operation","authors":"E. Buitrago, A. Mesemanolis, M. Andenna, C. Papadopoulos, C. Corvasce, J. Vobecký, Munaf T. A. Rahimo","doi":"10.1109/ISPSD.2019.8757638","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757638","url":null,"abstract":"Different state-of-the-art buffer concepts compatible with ≥ 200 mm diameter, thin wafer technology ($< 200 boldsymbol{mu} mathbf{m}$) have been optimized in enhanced planar insulated gate bipolar transistor (IGBT) technology for 1200 V and 1700 V, 150 A rated, 13.6 x 13.6 mm2 devices and evaluated with the goal of reducing leakage currents to enable a stable operation up to $mathbf{T}_{mathbf{j}}=200 {{}^{circ}mathbf{C}}$. With the maximum punch through (MPT) ultra-thin field stop design in particular, we can produce devices with the lowest leakage currents up to $mathbf{T}_{mathbf{j}}=200 {{}^{circ}mathbf{C}}$. These devices were found to provide rugged RBSOA and soft switching, can withstand short circuit pulses as long as $10 boldsymbol{mu}mathbf{s}$ and be thermally stable at $mathbf{T}_{mathbf{j}}=200 {{}^{circ}mathbf{C}}$.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128827937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design Method and Mechanism Study of LDMOS to Conquer Stress Induced Degradation of Leakage Current and HTRB Reliability LDMOS克服泄漏电流应力退化和HTRB可靠性的设计方法及机理研究
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757670
K. Komatsu, T. Kinoshita, S. Shioda, Toshihiro Sakamoto, K. Kimura, Koji Yonemura, F. Matsuoka, Keita Takahashi, Akihiro Urata, Shoichi Sakaguchi, Takahito Nagamatsu
{"title":"Design Method and Mechanism Study of LDMOS to Conquer Stress Induced Degradation of Leakage Current and HTRB Reliability","authors":"K. Komatsu, T. Kinoshita, S. Shioda, Toshihiro Sakamoto, K. Kimura, Koji Yonemura, F. Matsuoka, Keita Takahashi, Akihiro Urata, Shoichi Sakaguchi, Takahito Nagamatsu","doi":"10.1109/ISPSD.2019.8757670","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757670","url":null,"abstract":"8V NchLDMOS, which has an enough tolerance against both a leakage current (Idss) increase and high temperature reverse bias (HTRB) degradation is proposed. Dislocation growth, which results in Idss increase and has a negative influence on HTRB reliability, occurs because of a high-dose ion implantation and/or mechanical stress due to shallow trench isolation (STI). The studied 8V NchLDMOS was developed by taking into account the mechanism understanding to prevent the dislocation growth affecting the device characteristics, and as a result, achieved a competitive low resistance ($mathbf{RonA}=1.67mathbf{m}mathbf{Omega}.mathbf{mm}^{2}$).","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127084304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effects of Substrate Termination on Reverse-bias Stress Reliability of Normally-off Lateral GaN-on-Si MIS-FETs 衬底终止对常关侧GaN-on-Si misfet反偏置应力可靠性的影响
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757600
M. Hua, Song Yang, Zheyang Zheng, Jin Wei, Zhaofu Zhang, K. J. Chen
{"title":"Effects of Substrate Termination on Reverse-bias Stress Reliability of Normally-off Lateral GaN-on-Si MIS-FETs","authors":"M. Hua, Song Yang, Zheyang Zheng, Jin Wei, Zhaofu Zhang, K. J. Chen","doi":"10.1109/ISPSD.2019.8757600","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757600","url":null,"abstract":"In this work, reliability characterization under reverse-bias (i.e. off-state with high $boldsymbol{V}_{mathbf{DS}}$) stress was conducted on the E-mode GaN MIS-FETs with different substrate terminations. The MIS-FETs with a floating substrate exhibit stronger $boldsymbol{V}_{mathbf{TH}}$ instability than those with a grounded substrate. A non-monotonic dependence of $boldsymbol{V}_{mathbf{TH}}$ shifts on the positive substrate bias was also observed. The underlying mechanisms are proposed to be the impacts of positive substrate bias on holes drift during long-term reverse-bias stress.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121061469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High Performance GaN-on-Si Power Devices with Ultralow Specific On-resistance Using Novel Strain Method Fabricated on 200 mm CMOS-Compatible Process Platform 采用新型应变法在200 mm cmos兼容工艺平台上制备超低比导通电阻的高性能GaN-on-Si功率器件
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757694
R. Wong, H. Chiu, J. H. Zhang, C. Zhou, Thomas Zhao, Y. Wu, H. Liao, Simon He, A. Zhang, Y. Zou, Seiya Li, Martin Zhang, Marissa Wu, John Lee, P. Chen, A. Xie, Jeff Zhang
{"title":"High Performance GaN-on-Si Power Devices with Ultralow Specific On-resistance Using Novel Strain Method Fabricated on 200 mm CMOS-Compatible Process Platform","authors":"R. Wong, H. Chiu, J. H. Zhang, C. Zhou, Thomas Zhao, Y. Wu, H. Liao, Simon He, A. Zhang, Y. Zou, Seiya Li, Martin Zhang, Marissa Wu, John Lee, P. Chen, A. Xie, Jeff Zhang","doi":"10.1109/ISPSD.2019.8757694","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757694","url":null,"abstract":"A novel strain engineering is reported to realize enhancement-mode high electron mobility transistors (HEMTs) with ultralow specific on-resistance ($boldsymbol{R}_{mathbf{on},mathbf{sp}}$) fabricated on 200 mm CMOS-compatible process platform. In this scheme, a strain enhancement layer deposited on the access region of HEMT by a low cost CVD process is demonstrated to reduce $boldsymbol{R}_{mathbf{on},mathbf{sp}}$. As comparing to 100 V-rated HEMT without the strain layer, HEMT with the strain layer features comparable $boldsymbol{V}_{mathbf{th}}$ of +1.5 V but significant $boldsymbol{R}_{mathbf{on},mathbf{sp}}$ reduction of 24% and 28% at ambient temperatures of 25 °C and 150 °C, respectively. The proposed device exhibits the off-state drain-to-source breakdown voltage increases about 12%. System verification shows that high efficiency of 92.7% which is higher than the state-of-art Si MOSFET about 3% with stable burn-in performance. This work achieves a record low $boldsymbol{R}_{mathbf{on},mathbf{sp}}$ in 100 V rating commercially available GaN and Si power transistors.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123398591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
100-V Class Two-step-oxide Field-Plate Trench MOSFET to Achieve Optimum RESURF Effect and Ultralow On-resistance 100v级两步氧化场极板沟槽MOSFET，实现最佳的RESURF效果和超低导通电阻
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757615
Kenya Kobayashi, Hiroaki Kato, Toshifumi Nishiguchi, Saya Shimomura, Tetsuya Ohno, T. Nishiwaki, Kikuo Aida, Kentaro Ichinoseki, Kohei Oasa, Y. Kawaguchi
{"title":"100-V Class Two-step-oxide Field-Plate Trench MOSFET to Achieve Optimum RESURF Effect and Ultralow On-resistance","authors":"Kenya Kobayashi, Hiroaki Kato, Toshifumi Nishiguchi, Saya Shimomura, Tetsuya Ohno, T. Nishiwaki, Kikuo Aida, Kentaro Ichinoseki, Kohei Oasa, Y. Kawaguchi","doi":"10.1109/ISPSD.2019.8757615","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757615","url":null,"abstract":"We propose a 100-V class two-step-oxide Field-Plate MOSFET (2-step FP-MOSFET), which is formed by two steps of thick-oxide to simplify the structure and fabrication process. By optimizing design parameters, we reveal the 2-step FP-MOSFET can achieve sufficient RESURF (Reduced Surface Field) effect and an ultralow specific on-resistance ($boldsymbol{R}_{mathbf{ON}}boldsymbol{A}$). Measurement results showed breakdown voltage of 109.9 V and the $boldsymbol{R}_{mathbf{ON}}boldsymbol{A}$ of 27.7 mohm·mm2 with good process controllability. Moreover, as figure-of-merit of the 2-step FP-MOSFET, $boldsymbol{R}_{mathbf{ON}}cdot boldsymbol{Q_{g}}$ and $boldsymbol{R}_{mathbf{ON}}cdot boldsymbol{Q_{sw}}$ were reduced by 27.1% and 4.7%, respectively, compared with conventional one. Power loss estimation is also discussed by simple calculation.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127362565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
The Development of a 1200V/400A SiC Hybrid Module 1200V/400A SiC混合模块的研制
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757655
P. Ning, Tianshu Yuan, Han Cao, Lei Li, Yuhui Kang
{"title":"The Development of a 1200V/400A SiC Hybrid Module","authors":"P. Ning, Tianshu Yuan, Han Cao, Lei Li, Yuhui Kang","doi":"10.1109/ISPSD.2019.8757655","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757655","url":null,"abstract":"Hybrid switch (HyS) combines low conduction loss of Si IGBT and low switching loss of SiC MOSFET. The cost of HyS is close to pure Si IGBT. The promising high performances of HyS will bring considerable achievement to enhance power density of a converter system. In this paper, a SiC/Si HyS based 1200 V/400 A three phase module was developed, and was tested in a motor drive.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124413373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dynamic Threshold Voltage in $p$-GaN Gate HEMT p -GaN栅极HEMT的动态阈值电压
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757602
Jin Wei, Han Xu, Ruiliang Xie, Meng Zhang, Hanxing Wang, Yuru Wang, Kailun Zhong, M. Hua, Jiabei He, K. J. Chen
{"title":"Dynamic Threshold Voltage in $p$-GaN Gate HEMT","authors":"Jin Wei, Han Xu, Ruiliang Xie, Meng Zhang, Hanxing Wang, Yuru Wang, Kailun Zhong, M. Hua, Jiabei He, K. J. Chen","doi":"10.1109/ISPSD.2019.8757602","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757602","url":null,"abstract":"The <tex>$p$</tex>-GaN gate HEMT with a Schottky gate contact is studied in this work. The threshold voltage (<tex>$boldsymbol{V}_{mathbf{th}}$</tex>) of the device is found to have a dynamic nature. When the device experiences a high drain voltage <tex>$V_{text{DSQ}}$</tex>, the gate-to-drain capacitance <tex>$C_{text{GD}}$</tex> is charged to <tex>$boldsymbol{Q}_{mathbf{GD}}(boldsymbol{V}_{mathbf{DSQ}})$</tex>. The negative part of <tex>$boldsymbol{Q}_{mathbf{GD}}(boldsymbol{V}_{mathbf{DSQ}})$</tex> is mainly located in the <tex>$p$</tex>-GaN layer. When drain voltage drops to a lower value <tex>$V_{text{DSM}}$</tex>, the non-equilibrium charges <tex>$Delta boldsymbol{Q}_{mathbf{GD}}=boldsymbol{Q}_{mathbf{GD}}(boldsymbol{V}_{mathbf{GDQ}})-boldsymbol{Q}_{mathbf{GD}}(boldsymbol{V}_{mathbf{GDM}})$</tex> cannot be effectively released, since the discharging current is blocked by the reversely biased metal/<tex>$p$</tex>-GaN Schottky junction and <tex>$boldsymbol{p}$</tex>-GaN/2DEG PN junction. An extra <tex>$V_{text{GS}}$</tex> is required to counteract the non-equilibrium <tex>$Delta boldsymbol{Q}_{mathbf{GD}}$</tex>, resulting in a change of <tex>$boldsymbol{V}_{mathbf{th}}$</tex>. The change in <tex>$boldsymbol{V}_{mathbf{th}}$</tex> is well predictable by its linear relationship to <tex>$Delta boldsymbol{Q}_{mathbf{GD}}$</tex>. During switching operation, <tex>$boldsymbol{V}_{mathbf{th}}$</tex> is adaptive along the load line. Without considering the dynamic <tex>$boldsymbol{V}_{mathbf{th}}$</tex> effect, there exist large discrepancies in switching transients between the modelled and the experimental results. Incorporation of the dynamic <tex>$boldsymbol{V}_{mathbf{th}}$</tex> in device model result in greatly enhanced accuracy in simulated transient behavior.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123162776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Failure Mechanism Analysis of SiC MOSFETs in Unclamped Inductive Switching Conditions 非箝位电感开关条件下SiC mosfet失效机理分析
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757657
Na Ren, Kang L. Wang, Jiupeng Wu, Hongyi Xu, Kuang Sheng
{"title":"Failure Mechanism Analysis of SiC MOSFETs in Unclamped Inductive Switching Conditions","authors":"Na Ren, Kang L. Wang, Jiupeng Wu, Hongyi Xu, Kuang Sheng","doi":"10.1109/ISPSD.2019.8757657","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757657","url":null,"abstract":"In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) tests are investigated and compared with that of Si IGBT. The experimental results show that the avalanche energy of SiC MOSFET is only 30% that of Si IGBT due to the much smaller chip size (1/7 that of Si IGBT). To improve the avalanche capability of SiC MOSFET, the failure mechanism is analyzed. First, junction temperature in the UIS test is calculated through modeling. The maximum junction temperatures reach 650 K and 490 K in SiC MOSFET and Si IGBT, respectively. Then, BJT latch-up probability is analyzed with an analytical model. It is demonstrated that BJT latch-up can be triggered at the failure temperature (650 K) in SiC MOSFET, whereas it can be eliminated in Si IGBT due to the much deeper P+ body structure. Based on the analyses, the device structure optimization is proposed for SiC MOSFET to prevent the BJT latch-up and enable avalanche capability improvement.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"7 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121009565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Demonstration of Electron/Hole Injections in the Gate of $p$-GaN/AlGaN/GaN Power Transistors and Their Effect on Device Dynamic Performance p -GaN/AlGaN/GaN功率晶体管栅极中电子/空穴注入及其对器件动态性能的影响
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757614
Xi Tang, Baikui Li, Jun Zhang, Hui Li, Jisheng Han, N. Nguyen, S. Dimitrijev, Jiannong Wang
{"title":"Demonstration of Electron/Hole Injections in the Gate of $p$-GaN/AlGaN/GaN Power Transistors and Their Effect on Device Dynamic Performance","authors":"Xi Tang, Baikui Li, Jun Zhang, Hui Li, Jisheng Han, N. Nguyen, S. Dimitrijev, Jiannong Wang","doi":"10.1109/ISPSD.2019.8757614","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757614","url":null,"abstract":"In this work, we demonstrated the electron/hole injections in the gate of $boldsymbol{p}$-GaN/AlGaN/GaN power transistors at forward gate bias by capturing the electroluminescence (EL) emission from the gate region. The EL included both visible and ultraviolet (UV) luminescence. The dynamic switching tests were carried out to investigate the effect of electron and hole injections on device performances. The electron injection and trapping at the forward gate bias caused positive threshold voltage shift, while the injection of holes into the GaN channel induced the emission of the UV light and the resulting leakage current increase in the device.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122657723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Trading Off between Threshold Voltage and Subthreshold Slope in AlGaN/GaN HEMTs with a p-GaN Gate 带p-GaN栅极的AlGaN/GaN hemt中阈值电压和亚阈值斜率的权衡
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757629
B. Bakeroot, S. Stoffels, N. Posthuma, D. Wellekens, S. Decoutere
{"title":"Trading Off between Threshold Voltage and Subthreshold Slope in AlGaN/GaN HEMTs with a p-GaN Gate","authors":"B. Bakeroot, S. Stoffels, N. Posthuma, D. Wellekens, S. Decoutere","doi":"10.1109/ISPSD.2019.8757629","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757629","url":null,"abstract":"The measured values of the threshold voltage of AlGaN/GaN high-electron-mobility transistors (HEMTs) with a p-GaN gate are generally more positive than what is expected from a classical HEMT. The transfer characteristics exhibit subthreshold slopes which are higher compared to the standard 60 mV per decade at room temperature. The higher threshold voltage values and subthreshold slopes are related to the specific structure of the p-GaN gate, consisting of two back-to-back diodes. The dominating diode—either the metal to p-GaN Schottky diode or the p-GaN/AlGaN barrier/GaN channel diode—dictates how much gate current flows, determines the subthreshold behavior, and, thus also the threshold voltage. The trade-off between the threshold voltage and the subthreshold slope is discussed revealing the intricate dynamic relation between those two device metrics and the gate leakage current.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117312346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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