High Performance GaN-on-Si Power Devices with Ultralow Specific On-resistance Using Novel Strain Method Fabricated on 200 mm CMOS-Compatible Process Platform

Abstract

A novel strain engineering is reported to realize enhancement-mode high electron mobility transistors (HEMTs) with ultralow specific on-resistance ($\boldsymbol{R}_{\mathbf{on},\mathbf{sp}}$) fabricated on 200 mm CMOS-compatible process platform. In this scheme, a strain enhancement layer deposited on the access region of HEMT by a low cost CVD process is demonstrated to reduce $\boldsymbol{R}_{\mathbf{on},\mathbf{sp}}$. As comparing to 100 V-rated HEMT without the strain layer, HEMT with the strain layer features comparable $\boldsymbol{V}_{\mathbf{th}}$ of +1.5 V but significant $\boldsymbol{R}_{\mathbf{on},\mathbf{sp}}$ reduction of 24% and 28% at ambient temperatures of 25 °C and 150 °C, respectively. The proposed device exhibits the off-state drain-to-source breakdown voltage increases about 12%. System verification shows that high efficiency of 92.7% which is higher than the state-of-art Si MOSFET about 3% with stable burn-in performance. This work achieves a record low $\boldsymbol{R}_{\mathbf{on},\mathbf{sp}}$ in 100 V rating commercially available GaN and Si power transistors.