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2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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Performance and Reliability Co-design of LDMOS-SCR for Self-Protected High Voltage Applications On-Chip 片上自保护高电压应用的LDMOS-SCR性能与可靠性协同设计
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757641
N. K. Kranthi, B. Kumar, A. Salman, G. Boselli, M. Shrivastava
{"title":"Performance and Reliability Co-design of LDMOS-SCR for Self-Protected High Voltage Applications On-Chip","authors":"N. K. Kranthi, B. Kumar, A. Salman, G. Boselli, M. Shrivastava","doi":"10.1109/ISPSD.2019.8757641","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757641","url":null,"abstract":"In this work we address turn-on vulnerability of conventional LDMOS-SCR devices under standard circuit operation window. This behavior is correlated with early ESD / SoA failure and power-to-fail scalability issue in HV LDMOS-SCR devices. The 3D TCAD is used to Develop physical insights into the performance and reliability limiters of LDMOS-SCR device. Different engineered designs are proposed to mitigate turn-on vulnerability and ESD power to fail scalability, while keeping channel performance and hot carrier degradation unaffected.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116310138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Power cycling capability of silicon low-voltage MOSFETs under different operation conditions 不同工作条件下硅低压mosfet的功率循环能力
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757631
C. Schwabe, P. Seidel, J. Lutz
{"title":"Power cycling capability of silicon low-voltage MOSFETs under different operation conditions","authors":"C. Schwabe, P. Seidel, J. Lutz","doi":"10.1109/ISPSD.2019.8757631","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757631","url":null,"abstract":"Silicon low-voltage MOSFETs with a breakdown voltage lower than 80 V were tested for lifetime estimation under different operation conditions. The on-state resistance for these devices is very low; therefore, a special power cycling method with switching and conduction losses is used to be able to reach high temperature swings. These results are compared with the power cycling capability of inverse diodes and MOSFETs with reduced gate voltage under standard test conditions. The results with switching losses indicate a significantly higher lifetime compared to the other operation conditions. A simulation was performed to investigate the behavior. The temperature and current density distribution differ extremely due to different temperature coefficients. This leads to lower thermal-mechanical stress for the devices in switched mode and therefore to a higher lifetime as well.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115869180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Alpha-Particle Shielding Effect of Thick Copper Plating Film on Power MOSFETs 厚镀铜膜对功率mosfet的α粒子屏蔽效应
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757695
T. Nishiwaki, Kohei Oasa, Kentaro Ichinoseki, Kikuo Aida, T. Ohguro, Y. Takada, Hideharu Kojima, Y. Kawaguchi
{"title":"Alpha-Particle Shielding Effect of Thick Copper Plating Film on Power MOSFETs","authors":"T. Nishiwaki, Kohei Oasa, Kentaro Ichinoseki, Kikuo Aida, T. Ohguro, Y. Takada, Hideharu Kojima, Y. Kawaguchi","doi":"10.1109/ISPSD.2019.8757695","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757695","url":null,"abstract":"We investigated characteristics impact of alpha-particles irradiation to power MOSFETs and demonstrated alpha-particle shielding effect of thick copper plating film on a power MOSFET. We used americium-241 alpha-source for irradiating alpha-particles to the surface of the power MOSFET die. Irradiation under gate-source bias caused threshold voltage (Vth) decrease due to generated trapped holes in gate oxide, however, no Vth shift occurred under drain–source bias. We found that sensitivity to alpha-particles depends on gate structures of trench or planar. Recovery behavior of Vth shift by gate bias or thermal annealing support the hole trapping model in the gate oxide. We evaluated alpha-particle shielding effect of thick copper plating film. We demonstrated more than 15 micrometer thick copper plating on the power MOSFET shielded alpha-particles successfully.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124212603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Die-attach on Copper by Pressureless Silver Sintering in Formic Acid 在甲酸中无压烧结银在铜上的模附
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757605
Meiyu Wang, Yijing Xie, Y. Mei, Xin Li, G. Lu
{"title":"Die-attach on Copper by Pressureless Silver Sintering in Formic Acid","authors":"Meiyu Wang, Yijing Xie, Y. Mei, Xin Li, G. Lu","doi":"10.1109/ISPSD.2019.8757605","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757605","url":null,"abstract":"Sintered-silver die-attach has emerged as an excellent lead-free and reliable solution for high-temperature packaging. However, the most widely reported process involves pressure-assisted silver sintering on direct-bond-copper (DBC) substrates that are surface-finished with silver or gold plating, which adds to the cost of implementing this die-attach technology. One way to lower the cost is to die-attach on uncoated copper by pressure-less silver sintering. However, a challenge for this process is to prevent copper oxidation without significantly slowing the kinetics of silver sintering found in air. In this study, we explored the process of die-attach on copper by pressure-less silver sintering in a mixture atmosphere of formic-acid gas and air. The effects of oxygen fraction in the sintering atmosphere on the performance of an IGBT device bonded on an uncoated DBC substrate were examined. Strong, oxygen-free bond-line with die-shear strength over 30 MPa and excellent thermal and electrical performance of the packaged IGBT were obtained. The results in this study show the feasibility of a low-cost solution for implementing the silver sintering technology in manufacturing power semiconductor devices and/or modules.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131265703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A High-reliability Half-Bridge GaN FET Gate Driver with Advanced Floating Bias Control Techniques 采用先进浮动偏置控制技术的高可靠性半桥GaN FET栅极驱动器
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757625
Xin Ming, Xuan Zhang, Zhi-Wen Zhang, Li Hu, Yao Qin, Xu-dong Feng, Qi Zhou, Zhuo Wang, Bo Zhang
{"title":"A High-reliability Half-Bridge GaN FET Gate Driver with Advanced Floating Bias Control Techniques","authors":"Xin Ming, Xuan Zhang, Zhi-Wen Zhang, Li Hu, Yao Qin, Xu-dong Feng, Qi Zhou, Zhuo Wang, Bo Zhang","doi":"10.1109/ISPSD.2019.8757625","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757625","url":null,"abstract":"The advanced floating bias control techniques (FBCT) for GaN devices are proposed in this paper, which aims at solving negative voltage transient issues present at switching node of power stage during dead time. It adopts maximum power-supply tracking to reduce time delay of level shifter and active clamping for bootstrap voltage to avoid overvoltage conditions. This high-reliability half-bridge GaN gate driver has been fabricated in a $0.5boldsymbol{mu} mathbf{m}$ 80V HV CMOS process and occupies a chip area of $1699times 1522boldsymbol{mu} mathbf{m}^{2}$ where the active area of FBCT with internal bootstrap diode is $1350times 620boldsymbol{mu}mathbf{m}^{2}$. The response time of level shifter is only 1.97ns in the process of turning on high-side power switch. Transmission delay is small and there are no logic errors or latch-up issues in the gate driver due to the negative voltage transient. Bootstrap voltage ripple based on active clamping technique is well controlled over a wide frequency range (166mV@500kHz∼ 797mV@5MHz at $boldsymbol{C}_{mathbf{boot}}=0.1boldsymbol{mu}mathbf{F}$). The total quiescent current consumed by FBCT is only $90boldsymbol{mu} mathbf{A}$.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121307744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High-temperature Performance of 1.2 kV-class SiC Super Junction MOSFET 1.2 kv级SiC超级结MOSFET的高温性能
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757609
Yusuke Kobayashi, S. Kyogoku, T. Morimoto, T. Kumazawa, Yusuke Yamashiro, M. Takei, S. Harada
{"title":"High-temperature Performance of 1.2 kV-class SiC Super Junction MOSFET","authors":"Yusuke Kobayashi, S. Kyogoku, T. Morimoto, T. Kumazawa, Yusuke Yamashiro, M. Takei, S. Harada","doi":"10.1109/ISPSD.2019.8757609","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757609","url":null,"abstract":"SiC SJ MOSFETs had exhibited soft recovery characteristics at room temperature in comparison with that of non-SJ MOSFETs. In this study, the static and dynamic characteristics of the SiC SJ MOSFET at high temperature have been first demonstrated to clarify the mechanism of the soft recovery of the body-diode. The $boldsymbol{R_{onA}}$ at high temperature was drastically decreased by the SJ structure due to small drift resistance with suppressed injection level. The hard recovery characteristics are suppressed by the low injection level and large output capacitance ($boldsymbol{C_{oss}}$) compared with those in the Si SJ MOSFETs, indicating the great potential of SiC SJ MOSFET in various applications.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126081386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Experimental Demonstration on Superior Switching Characteristics of 1.2 kV SiC SWITCH-MOS 1.2 kV SiC开关mos优越开关特性的实验论证
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757628
R. Aiba, M. Okawa, T. Kanamori, H. Yano, N. Iwamuro, Yusuke Kobayashi, S. Harada
{"title":"Experimental Demonstration on Superior Switching Characteristics of 1.2 kV SiC SWITCH-MOS","authors":"R. Aiba, M. Okawa, T. Kanamori, H. Yano, N. Iwamuro, Yusuke Kobayashi, S. Harada","doi":"10.1109/ISPSD.2019.8757628","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757628","url":null,"abstract":"A 1.2kV silicon carbide (SiC) SBD-wall-integrated trench MOSFET (SWITCH-MOS) had been proposed and fabricated in order to solve body-PiN-diode related problems such as bipolar degradation and reverse recovery loss. In this paper, switching characteristics of turn-on and turn-off of the SWITCH-MOS are investigated and discussed in comparison with conventional trench MOSFET structures with p+ region at trench gate bottom (IE-UMOSFET) and without the p+ region (named “device A” in this paper). The SWITCH-MOS shows an extremely small turn-on loss and turn-off loss because of the high $boldsymbol{dV}/boldsymbol{dt}$ and little reverse recovery current. In addition, it is found that the SWITCH-MOS exhibits smaller turn-off loss than “device A” at almost the same $boldsymbol{dJ}/boldsymbol{dt}$, which means that drain surge voltage was suppressed effectively while keeping the smaller turn-off loss.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124979840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
High-performance normally-off tri-gate GaN power MOSFETs 高性能常关三栅GaN功率mosfet
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757690
Minghua Zhu, Jun Ma, L. Nela, E. Matioli
{"title":"High-performance normally-off tri-gate GaN power MOSFETs","authors":"Minghua Zhu, Jun Ma, L. Nela, E. Matioli","doi":"10.1109/ISPSD.2019.8757690","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757690","url":null,"abstract":"In this work, we present the investigation of the combination of gate recess and tri-gate structures to achieve high performance normally-off GaN-on-Si MOSFETs with high positive threshold voltage ($boldsymbol{V}_{mathbf{TH}}$), low specific on resistance ($boldsymbol{R}_{mathbf{ON},mathbf{SP}}$) and high output current ($boldsymbol{I}_{mathbf{D}}^{mathbf{max}}$). The excellent channel control capability offered by tri-gate structure led to a reduced OFF-state leakage current ($boldsymbol{I}_{mathbf{OFF}}$), higher ON/OFF ratio, smaller subthreshold slope ($boldsymbol{SS}$) compared to similar planar and recessed-gate devices. With gate to drain length ($boldsymbol{L}_{mathbf{GD}}$) of $20 boldsymbol{mu}mathbf{m}$, a hard $boldsymbol{V}_{mathbf{BR}}$ of 2050 V were achieved, along with a low $boldsymbol{R}_{mathbf{ON},mathbf{SP}}$ of $2.42 mathbf{m}mathbf{Omega}cdot mathbf{cm}^{2}$, which corresponds to a state-of-the-art figure of merit (FOM) of 1.73 GW/cm2. These results unveil the extraordinary prospects of tri-gate technology for future power electronics applications.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114509453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Integrated Gate Driver for E-mode GaN HEMTs with Active Clamping for Reverse Conduction Detection 一种用于反导检测有源箝位的e型GaN hemt集成栅极驱动器
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757616
Wei Jia Zhang, Yahui Leng, Jingshu Yu, Yu Shen Lu, ChuYao Cheng, W. Ng
{"title":"An Integrated Gate Driver for E-mode GaN HEMTs with Active Clamping for Reverse Conduction Detection","authors":"Wei Jia Zhang, Yahui Leng, Jingshu Yu, Yu Shen Lu, ChuYao Cheng, W. Ng","doi":"10.1109/ISPSD.2019.8757616","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757616","url":null,"abstract":"Detection of reverse-conduction in GaN-based switched-mode power converters is essential to reduce power loss and to protect the circuit from severe undershoot voltage. In this paper, an active clamping SenseFET circuit is proposed to measure the duration that the low-side GaN HEMT is in reverse-conduction and with protection from the high voltage at the switching node. The output of the SenseFET clamping circuit is processed by a custom designed gate driver IC. This IC is fabricated using TSMC's $0.18 boldsymbol{mu} mathbf{m}$ BCD GEN2 process for driving e-mode GaN power HEMTs with an on-chip closed-loop dead-time correction circuit. The one-step correction mode can optimize the dead-times for both the turn-on and turn-off edges in one switching cycle for switching frequencies of up to 10 MHz with 0.32 ns precision. This allow the power converters to maintain optimal conversion efficiency over the full output current range.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123896815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Effects of the HV-BIGT Design Elements on the High-Frequency Oscillation Instability during Short Circuit Transients HV-BIGT设计元件对短路瞬态高频振荡不稳定性的影响
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-19 DOI: 10.1109/ISPSD.2019.8757575
P. D. Reigosa, C. Papadopoulos, F. Iannuzzo, C. Corvasce, Munaf T. A. Rahimo
{"title":"Effects of the HV-BIGT Design Elements on the High-Frequency Oscillation Instability during Short Circuit Transients","authors":"P. D. Reigosa, C. Papadopoulos, F. Iannuzzo, C. Corvasce, Munaf T. A. Rahimo","doi":"10.1109/ISPSD.2019.8757575","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757575","url":null,"abstract":"The design elements of the Bi-mode Insulated Gate Transistor BIGT show that the combination of the high hole injection levels supplied from the collector together with the presence of a localized lifetime control at the MOS cells have brought improvements on the short circuit capability, strongly minimizing the high-frequency oscillations observed in IGBTs. The BIGT concept and the traditional IGBT structures have been compared under short circuit conditions to investigate the charge-field interactions at the MOS cells, triggering the oscillation mechanism. The effect of the lifetime control and the irradiation method on the short circuit capability is investigated.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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