Performance and Reliability Co-design of LDMOS-SCR for Self-Protected High Voltage Applications On-Chip

Abstract

In this work we address turn-on vulnerability of conventional LDMOS-SCR devices under standard circuit operation window. This behavior is correlated with early ESD / SoA failure and power-to-fail scalability issue in HV LDMOS-SCR devices. The 3D TCAD is used to Develop physical insights into the performance and reliability limiters of LDMOS-SCR device. Different engineered designs are proposed to mitigate turn-on vulnerability and ESD power to fail scalability, while keeping channel performance and hot carrier degradation unaffected.