2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)最新文献_第3页

Dynamic Key Updates for LUT Locked Design LUT锁定设计的动态密钥更新

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9839821

Jakub Słowik, Gregory Williams, Rummah Albashir, Anthony Samagio, Geraldine Shirley Nicholas, F. Saqib

引用次数: 1

Towards Attack Resilient Delay-Based Strong PUFs 基于攻击弹性延迟的强puf

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9839791

Nils Wisiol

引用次数: 1

SecSoC: A Secure System on Chip Architecture for IoT Devices SecSoC:物联网设备的安全片上系统架构

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9839995

Ayman Hroub, M. Elrabaa

{"title":"SecSoC: A Secure System on Chip Architecture for IoT Devices","authors":"Ayman Hroub, M. Elrabaa","doi":"10.1109/HOST54066.2022.9839995","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839995","url":null,"abstract":"IoT technology is finding new applications every day and everywhere in our daily lives. With that, come new use cases with new challenges in terms of device and data security. One of such challenges arises from the fact that many IoT devices/nodes are no longer being deployed on owners' premises, but rather on public or private property other than the owner's. With potential physical access to the IoT node, adversaries can launch many attacks that circumvent conventional protection methods. In this paper, we propose Secure SoC (SecSoC), a secure system-on-chip architecture that mitigates such attacks. This include logical memory dump attacks, bus snooping attacks, and compromised operating systems. SecSoC relies on two main mechanisms, (1) providing security extensions to the compute engine that runs the user application without changing its instruction set, (2) adding a security management unit (SMU) that provide HW security primitives for encryption, hashing, random number generators, and secrets store (keys, certificates, etc.). SecSoC ensures that no secret or sensitive data can leave the SoC IC in plaintext. SecSoC is being implemented in Bluespec System V erilog. The experimental results will reveal the area, power, and cycle time overhead of these security extensions. Overall performance (total execution time) will also be evaluated using IoT benchmarks.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134589657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient and Side-Channel Resistant Design of High-Security Ed448 on ARM Cortex-M4 基于ARM Cortex-M4的高安全性Ed448高效抗侧信道设计

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9839742

Mila Anastasova, Mojtaba Bisheh-Niasar, Hwajeong Seo, R. Azarderakhsh, Mehran Mozaffari Kermani

{"title":"Efficient and Side-Channel Resistant Design of High-Security Ed448 on ARM Cortex-M4","authors":"Mila Anastasova, Mojtaba Bisheh-Niasar, Hwajeong Seo, R. Azarderakhsh, Mehran Mozaffari Kermani","doi":"10.1109/HOST54066.2022.9839742","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839742","url":null,"abstract":"The demand for classical cryptography schemes continues to increase due to the exhaustive studies on their security. Thus, constant improvement of timing, power consumption, and memory requirements are needed for the most widely used classical Elliptic Curve Cryptography (ECC) primitives, suiting high-as well as low-end devices. In this work, we present the first implementation of the Edwards Curve Digital Signature Algorithm (EdDSA) based on the Ed448 targeting the ARM Cortex-M4-based STM32F407VG microcontroller, which forms a large part of the Internet of Things (IoT) world. We report timing and memory consumption results based on portable C and target-specific hand-crafted assembly code implementations of the low-level finite filed arithmetics. We optimize the high-level group operations by implementing the efficient scalar multiplication over the Ed448 isogenous map to reduce the computation complexity. Furthermore, we provide a side-channel analysis (SCA) and fault attack protected design by developing point randomization, scalar blinding techniques, and repeated signature, and evaluate the performance. Our optimized architecture performs a signature and verification in 39.88ms and 51.54ms, respectively, where SCA protection can be achieved at less than 6.4% cost of performance overhead.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130564264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

PUF-based Secure Test Wrapper Design for Network-on-Chip 基于puf的片上网络安全测试封装器设计

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9840115

Ying Zhang, Yuanxiang Li, Xin Chen, Jizhong Yang, Yifeng Hua, Jiaoyan Yao

引用次数: 1

A Lightweight Mutual Authentication Protocol Based on Physical Unclonable Functions 基于物理不可克隆功能的轻量级互认证协议

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9840132

Saeed Abdolinezhad, A. Sikora

引用次数: 2

Detecting Continuous Jamming Attack using Ultra-low Power RSSI Circuit 利用超低功耗RSSI电路检测持续干扰攻击

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9840209

Ankit Mittal, A. Shrivastava

引用次数: 2

Identification and Classification of Corrupted PUF Responses via Machine Learning 基于机器学习的损坏PUF响应识别与分类

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9839919

Reshmi Suragani, Emiliia Nazarenko, N. Anagnostopoulos, Nico Mexis, E. Kavun

{"title":"Identification and Classification of Corrupted PUF Responses via Machine Learning","authors":"Reshmi Suragani, Emiliia Nazarenko, N. Anagnostopoulos, Nico Mexis, E. Kavun","doi":"10.1109/HOST54066.2022.9839919","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839919","url":null,"abstract":"A Physical Unclonable Function (PUF) exploits de-vice manufacturing variations to extract a number of unique responses, each of which corresponds to a specific challenge, and use them for secret generation as well as authentication. However, these responses are often excessively noisy for authentication. In this study, in order to avoid using a complicated and costly Error Correction Code (ECC) in the context of a fuzzy extractor, we propose a Machine Learning (ML)-based classification technique that works accurately even in the presence of corrupted responses and we test it on an existing SRAM PUF dataset. In this approach, the SRAM power-up responses are transformed into 2D images in order to extract features from them for classification. With our proposed architecture, an accuracy of 97.34 % is achieved for “intact” noisy images. In addition, the presented ML model is successful in classifying responses even when a large part of them was corrupted. With our approach, the model can classify responses accurately with up to a 30 % loss in data. Finally, we also propose a proof-of-concept authentication technique using the relevant Convolutional Neural Network (CNN).","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115874438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Securing Hardware Accelerator during High-level Synthesis 在高级合成期间保护硬件加速器

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9840309

Dipanjan Roy, Sabiya Jani Shaik, Sonam Sharma

引用次数: 1

Practical Performance of Analog Attack Techniques 模拟攻击技术的实际性能

2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) Pub Date : 2022-06-27 DOI: 10.1109/HOST54066.2022.9839966

Vaibhav Venugopal Rao, Kyle Juretus, I. Savidis

{"title":"Practical Performance of Analog Attack Techniques","authors":"Vaibhav Venugopal Rao, Kyle Juretus, I. Savidis","doi":"10.1109/HOST54066.2022.9839966","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839966","url":null,"abstract":"The increasing number of vulnerabilities in analog circuits has motivated the development of novel security techniques that protect the analog supply chain. A variety of attacks including ones based on satisfiability modulo theory (SMT) and genetic algorithms (GA) have been executed on different analog circuits to evaluate the vulnerabilities of the added protection. However, the current attack techniques assume ideal conditions, where the attacker has complete knowledge of the IC except for the key used to obfuscate the circuit. In this paper, four different threat models are examined, where an adversary is assumed to have different levels of access to circuit and security information. The analysis of the attack performance on key-based parameter obfuscation is performed premised upon the level of information possessed by the adversary. The analog attack techniques are evaluated on five distinct circuit topologies, each implemented with different key sizes and obfuscated parameters. Through analysis of the results, a characterization of the advantages and disadvantages of the analog attack algorithms is provided.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"217 2‐3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132702860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0