Securing Hardware Accelerator during High-level Synthesis

Abstract

Performing Reverse Engineering (RE) on the Intellectual Property (IP) core of Hardware Accelerator (HA) becomes the first step of the attackers to launch a successful attack. This enables them to introduce hardware Trojan, create backdoors, cloning and counterfeit the IP core. In this work, a robust hardware obfuscation approach is proposed to generate a reverse engineering resilient hardware accelerator. The obfuscation is performed in three different ways during the scheduling phase of High-level Synthesis (HLS) by embedding key-controlled components. Unlike state-of-the-art approaches, a novel algorithm is developed to identify the suitable locations for embedding these key-controlled components to enhance the reverse engineering complexity. The proposed method incurs minimal average design cost overhead, i.e., 7% compared to the non-obfuscated design and achieves average design cost reduction by 12.1% compared to one closely related approach for key size 90.