{"title":"Partial Reconfiguration for Run-time Memory Faults and Hardware Trojan Attacks Detection","authors":"Ying Li, Lan Chen, Jian Wang, Guanfei Gong","doi":"10.1109/HOST54066.2022.9840090","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9840090","url":null,"abstract":"Embedded memory are important components in system-on-chip, which may be crippled by aging and wear faults or Hardware Trojan attacks to compromise run-time security. The current built-in self-test and pre-silicon verification lack efficiency and flexibility to solve this problem. To this end, we address such vulnerabilities by proposing a run-time memory security detecting framework in this paper. The solution builds mainly upon a centralized security detection controller for partially reconfigurable inspection content, and a static memory wrapper to handle access conflicts and buffering testing cells. We show that a field programmable gate array prototype of the proposed framework can pursue 16 memory faults and 3 types Hardware Trojans detection with one reconfigurable partition, whereas saves 12.7% area and 2.9% power overhead compared to a static implementation. This architecture has more scalable capability with little impact on the memory accessing throughput of the original chip system in run-time detection.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"WiP: Applicability of ISO Standard Side-Channel Leakage Tests to NIST Post-Quantum Cryptography","authors":"Markku-Juhani O. Saarinen","doi":"10.1109/HOST54066.2022.9839849","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839849","url":null,"abstract":"FIPS 140–3 is the main standard defining security requirements for cryptographic modules in U.S. and Canada; commercially viable hardware modules generally need to be compliant with it. The scope of FIPS 140–3 will also expand to the new NIST Post-Quantum Cryptography (PQC) standards when migration from older RSA and Elliptic Curve cryptography begins. FIPS 140–3 mandates the testing of the effectiveness of “non-invasive attack mitigations”, or side-channel attack coun-termeasures. At higher security levels 3 and 4, the FIPS 140–3 side-channel testing methods and metrics are expected to be those of ISO 17825, which is based on the older Test Vector Leakage Assessment (TVLA) methodology. We discuss how to apply ISO 17825 to hardware modules that implement lattice-based PQC standards for public-key cryptography - Key Encapsulation Mechanisms (KEMs) and Digital Signatures. We find that simple “random key” vs. “fixed key” tests are unsatisfactory due to the close linkage between public and private components of PQC keypairs. While the general statistical testing approach and requirements can remain consistent with older public-key algorithms, a non-trivial challenge in creating ISO 17825 testing procedures for PQC is the careful design of test vector inputs so that only relevant Critical Security Parameter (CSP) leakage is captured in power, electromagnetic, and timing measurements.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121481966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Safeguarding Unmanned Aerial Vehicles Against Side Channel Analysis Via Motor Noise Injection","authors":"Timothy Radtke, Cristinel Ababei","doi":"10.1109/HOST54066.2022.9839837","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839837","url":null,"abstract":"We first investigate the efficacy of side channel anal-ysis (SCA) based attacks to recover the encryption key from an unmanned aerial vehicle (UAV). We then propose a method based on noise injection to safeguard against this type of attack. The proposed noise injection method is unique because it prioritizes low power consumption and uses as a noise source the motors of the UAV system. The effectiveness of the proposed method is demonstrated through experiments on a real quadcopter. It is found that when noise injection is not applied, the encryption key can be recovered through correlation power analysis. In contrast, the same key is not recoverable when the proposed noise injection method is applied. The implemented solution is efficient and does not negatively effect the flight stability or control of the UAV because its execution time overhead is negligible inside the control loop. In addition, it consumes a negligible amount of power. These results demonstrate that mitigation of SCA attacks without expanding the complexity or negatively effecting the flight operations of drones is achievable.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123892443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SpecPref: High Performing Speculative Attacks Resilient Hardware Prefetchers","authors":"Tarun Solanki, Biswabandan Panda","doi":"10.1109/HOST54066.2022.9839828","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839828","url":null,"abstract":"With the inception of the Spectre attack in 2018, microarchitecture mitigation strategies propose secure cache hi-erarchies that do not leak the speculative state. Among many mitigation strategies, MuonTrap, proposes an efficient, secure cache hierarchy that provides speculative attack resiliency with minimum performance slowdown. Hardware prefetchers play a significant role in improving application performance by fetching and bringing data and instructions into caches before time. To prevent hardware prefetchers from leaking information about the speculative blocks brought into the cache, MuonTrap trains and triggers hardware prefetchers on the committed instruction streams, eliminating speculative state leakage. We find that on-commit prefetching can lead to significant performance slowdown as high as 20.46 % (primarily because of prefetch timeliness issues), making hardware prefetchers less effective. We propose Speculative yet Secure Prefetching (SpecPref), enhancements on top of the MuonTrap hierarchy that allows prefetching both on-commit and speculatively. We focus on improving the performance slowdown with the state-of-the-art hardware prefetchers without compromising the security guarantee provided by the MuonTrap implementation and provide an average performance slowdown of 1.17%.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114973617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network","authors":"A. Roohi, Shaahin Angizi","doi":"10.1109/HOST54066.2022.9839959","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839959","url":null,"abstract":"Deep neural networks (DNNs) have shown their great capability of surpassing human performance in many areas. With the help of quantization, artificial intelligence (AI) powered devices are ubiquitously deployed. Yet, the easily accessible AI-powered edge devices become the target of malicious users who can deteriorate the privacy and integrity of the inference process. This paper proposes two adversarial attack scenarios, including three threat models, which crush local binary pattern networks (LBPNet). These attacks can be applied maliciously to flip a limited number of susceptible bits in kernels within the system's shared memory. The threat could be driven through the Row-Hammer attack and significantly drops the model's accuracy. Our preliminary simulation results demonstrate flipping only the most significant bit of the first LBP layer decreases the accuracy from 99.51 % down to 18 % on the MNIST data-set. We then briefly discuss potential hardware/software -oriented defense mechanisms as countermeasures to such attacks.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125573757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Novel Attack on Machine-Learning Resistant Physical Unclonable Functions","authors":"D. Canaday, W. A. S. Barbosa, A. Pomerance","doi":"10.1109/HOST54066.2022.9839670","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839670","url":null,"abstract":"Many of today's proposed designs for strong physical unclonable functions (PUFs) are constructed from strong PUF building blocks that are known to be themselves vulnerable to machine-learning (ML) attacks, such as the Arbiter PUF or Ring Oscillator PUF. These designs aim to make the global design ML-resistant by obscuring the true challenge and/or responses corresponding to the vulnerable building blocks, thereby making it more difficult for ML attacks to infer underlying model parameters. In this work, we propose a model-free ML attack, inspired by deep learning-based image imputation algorithms, that successfully breaks these popular countermeasures. Our attack is unique in that it uses not only the observed challenge-response pairs (CRPs) of the device being attacked but also uses CRPs collected from other PUFs of the same type, which results in improved bit-error rates (BERs). We show that our attack breaks several proposed ML-resistant PUF architectures based on obfuscation of vulnerable strong PUF building blocks.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133000792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Secuirty Metrics for Logic Circuits","authors":"Ruben Purdy, Danielle Duvalsaint, R. D. Blanton","doi":"10.1109/HOST54066.2022.9840239","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9840239","url":null,"abstract":"Any type of engineered design requires metrics for trading off both desirable and undesirable properties. For integrated circuits, typical properties include circuit size, performance, power, etc., where for example, performance is a desirable property and power consumption is not. Security metrics, on the other hand, are extremely difficult to develop because there are active adversaries that intend to compromise the protected circuitry. This implies metric values may not be static quantities, but instead are measures that degrade depending on attack effectiveness. In order to deal with this dynamic aspect of a security metric, a general attack model is proposed that enables the effectiveness of various security approaches to be directly compared in the context of an attack. Here, we describe, define and demonstrate that the metrics presented are both meaningful and measurable.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128114860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Security Threats and Countermeasure Deployment Using Partial Reconfiguration in FPGA CAD Tools","authors":"Sandeep Sunkavilli, Qiaoyan Yu","doi":"10.1109/HOST54066.2022.9839731","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839731","url":null,"abstract":"FPGAs have gained increasing popularity and usage in recent years and they have been widely used in mission-critical applications. To save the cost of computation hardware, FPGAs are even made available by cloud service providers. To improve the flexibility of dynamic programming and reduce the FPGA compile time, a Partial Reconfiguration (PR) feature has been enabled in the FPGA development environment. PR is performed by FPGA CAD tools, which do not only provide new functionality for design programmers but also open new attack surfaces for adversaries. In this work, we first illustrate how PR can be used to thwart the attacks that facilitate reserve engineering and nullify the authentication module. We also analyze the potential security threats that PR could bring to FPGA design flow.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127773151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Modeling Attack on the Sub-threshold Current Array PUF","authors":"Yun Liu, Yongliang Chen, Xiaole Cui","doi":"10.1109/HOST54066.2022.9839861","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9839861","url":null,"abstract":"Physical unclonable function (PUF) is regarded as the root of trust of integrated circuits. However, the modeling attack poses a great threat to the PUF circuits. Recently, the non-linear characteristic in the sub-threshold region of MOSFET transistors was applied to construct the PUF circuit against the modeling attacks. This work attacks the sub-threshold current array PUF (SCA-PUF) using an artificial neural network (ANN) model. The ANN model is deliberately designed based on the working principle of the target PUF. In the attacks, the linear functions are used to approximate the nonlinear characteristics of the sub-threshold region, by using the first-order Taylor expansion. The attack results show that the prediction accuracy of the ANN based method reaches 94.4% with 1000 training CRPs, whereas the prediction accuracy of LR algorithm and SVM algorithm are only 75.2% and 77.8%, respectively. It shows that the SCA-PUF is also vulnerable to the modeling attacks, and the ANN method is more powerful compared with the LR and SVM algorithms for the attacks of SCA-PUF.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132153436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the Feasibility of Training-time Trojan Attacks through Hardware-based Faults in Memory","authors":"Kunbei Cai, Zhenkai Zhang, F. Yao","doi":"10.1109/HOST54066.2022.9840266","DOIUrl":"https://doi.org/10.1109/HOST54066.2022.9840266","url":null,"abstract":"Training-time trojan attacks have been one of the major security threats that can tamper integrity of deep learning models. Existing trojan attacks either require poisoning of the training dataset or depend on control of the training process. In this paper, we investigate the practicality of leveraging hardware-based fault attacks to introduce trojan in deep neural networks (DNNs) at training time. Specifically, we consider a memory-based fault injection using the rowhammer attack vector. We propose a new attack framework where the adversary injects faults to the feature map of DNN models during training. We investigate the impact of bit flips in feature maps and derive a bit flip strategy that enables the victim model to associate a perturbed feature map pattern with a target label without impacting the prediction of normal inputs. We further propose an input trigger identification algorithm that obtains the trigger pattern for the trojaned model at inference time. Our evaluation shows that our attack can trojan DNN models with very high attack success rate. Our work highlights the importance of understanding the impact of hardware-based fault attacks in machine learning training.","PeriodicalId":222250,"journal":{"name":"2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114710525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}