Security Threats and Countermeasure Deployment Using Partial Reconfiguration in FPGA CAD Tools

Abstract

FPGAs have gained increasing popularity and usage in recent years and they have been widely used in mission-critical applications. To save the cost of computation hardware, FPGAs are even made available by cloud service providers. To improve the flexibility of dynamic programming and reduce the FPGA compile time, a Partial Reconfiguration (PR) feature has been enabled in the FPGA development environment. PR is performed by FPGA CAD tools, which do not only provide new functionality for design programmers but also open new attack surfaces for adversaries. In this work, we first illustrate how PR can be used to thwart the attacks that facilitate reserve engineering and nullify the authentication module. We also analyze the potential security threats that PR could bring to FPGA design flow.