Dynamic Key Updates for LUT Locked Design

Abstract

Given the massive influx of technological advancement, semiconductor companies have moved to offshore foundries for manufacturing and utilize third party Intellectual Property (3PIP) during design and integration processes. 3PIP improves design time, cost, and adaptability of intricate and ever-changing design flows of SoCs, however, it also opens the door for malicious actors to sabotage the semiconductor ecosystem by IP theft, trojans and counterfeit chips. We propose a secure design flow for 3PIP integration for the FPGA platform that enables the key update process for key locks during the lifecycle of the FPGA based 3PIP. The paper demonstrates the design process of partial bitstreams of secured benchmarks, implement LUT level key gates dynamic partial reconfiguration, and secure architecture to enable key provisioning during runtime.