2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design最新文献

Assertion-Based Design with Horus 基于断言的设计与Horus

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547691

Y. Oddos, K. Morin-Allory, D. Borrione

引用次数: 15

From Data to Events: Checking Properties on the Control of a System 从数据到事件:检查系统控制的属性

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547682

Christophe Jacquet, Frédéric Boulanger, Dominique Marcadet

引用次数: 4

Rule-Based Approaches for Equivalence Checking of SpecC Programs 基于规则的spec程序等价检验方法

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547685

S. Shankar, M. Fujita

引用次数: 4

H.264 Decoder: A Case Study in Multiple Design Points H.264解码器:在多个设计点的案例研究

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547707

Kermin Fleming, Chun-Chieh Lin, Nirav H. Dave, Arvind, Gopal Raghavan, Jamey Hicks

{"title":"H.264 Decoder: A Case Study in Multiple Design Points","authors":"Kermin Fleming, Chun-Chieh Lin, Nirav H. Dave, Arvind, Gopal Raghavan, Jamey Hicks","doi":"10.1109/MEMCOD.2008.4547707","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547707","url":null,"abstract":"H.264, a state-of-the-art video compression standard, is used across a range of products from cellphones to HDTV. These products have vastly different performance, power and cost requirements, necessitating different hardware-software solutions for H.264 decoding. We show that a design methodology and associated tools which support synthesis from high-level descriptions and which allow modular refinement throughout the design cycle, can share the majority of design effort across multiple design points. Using Bluespec SystemVerilog, we have created a variety of designs for the H.264 decoder tuned to support decoding at resolutions ranging from QCIF video (176 times 144 @ 15 frames/second) to 1080p video ((1280 times 1080)p @60 frames/second) in a 180 nm process. Some of these design points require major transformations of pipelining to increase performance or to reduce area. We also explore several common design issues surrounding memory structures, such as caches and on-chip vs. off-chip memories. We believe the design methodology used in this paper is directly applicable to many IP blocks involving algorithmic specifications. The same design capabilities also permit rapid microarchitecture exploration and changes in RTL late in the design process even in non-algorithmic IP blocks.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125747319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Vacuity Analysis by Fault Simulation 故障模拟真空分析

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547683

L. D. Guglielmo, F. Fummi, G. Pravadelli

引用次数: 4

Classification of General Data Flow Actors into Known Models of Computation 一般数据流参与者在已知计算模型中的分类

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547699

C. Zebelein, J. Falk, C. Haubelt, J. Teich

引用次数: 34

Directed-Logical Testing for Functional Verification of Microprocessors 微处理器功能验证的定向逻辑测试

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547694

Michael Katelman, J. Meseguer, Santiago Escobar

{"title":"Directed-Logical Testing for Functional Verification of Microprocessors","authors":"Michael Katelman, J. Meseguer, Santiago Escobar","doi":"10.1109/MEMCOD.2008.4547694","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547694","url":null,"abstract":"The length of the microprocessor development cycle is largely determined by functional verification, where contemporary practice relies primarily on constraint-based random stimulus generation to drive a simulation-based methodology. However, formal methods are, in particular, gaining wider adoption and are seen as having potential to bridge large gaps left by current techniques. And many gaps still remain. In this paper we propose directed- logical testing: a new method of stimulus generation based on purely logical techniques (i.e. formal methods). As far as we know, our methodology represents the first end-to-end mathematical formalization of the stimulus generation problem. Therefore, a major contribution of this paper is the definition of a class of logical propositions that relate the actual microprocessor implementation, the assembly program stimulus, and a coverage goal. These propositions are given in rewriting logic, and use the idea of rewriting semantics to automatically formalize within a common logical framework the microprocessor implementation and assembly programs. To solve these propositions, we demonstrate how narrowing and user-defined narrowing strategies can be used as a scalable logical framework. In addition, we describe two classes of effective strategies that can be used for many microprocessors and common coverage goals. Finally, we describe a prototype tool implementation and present empirical data to demonstrate the feasibility of our methodology. Since narrowing and user-defined narrowing strategies within rewriting logic do not yet have tool support, our prototype tool uses standard rewriting and user-defined rewriting strategies to simulate narrowing.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122596295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design Contest 硬件加速加密合并排序:MEMOCODE 2008设计竞赛

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547705

VJ Sananda

引用次数: 1

High-throughput Pipelined Mergesort 高吞吐量流水线合并排序

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547704

Kermin Fleming, Myron King, Man Cheuk Ng, Asif Khan, M. Vijayaraghavan

引用次数: 12

Latency-Insensitive Hardware/Software Interfaces 延迟不敏感的硬件/软件接口

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547689

G. Hoover, F. Brewer, C. Gill

引用次数: 0