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2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design最新文献

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Infinite State Model Checking with Arithmetic Constraints 基于算术约束的无限状态模型检验
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547697
T. Bultan
{"title":"Infinite State Model Checking with Arithmetic Constraints","authors":"T. Bultan","doi":"10.1109/MEMCOD.2008.4547697","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547697","url":null,"abstract":"","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"8 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116801841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation Systems bisemulator 2.0:一个基于布尔方程系统的动态等价校验器
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547690
Radu Mateescu, Emilie Oudot
{"title":"Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation Systems","authors":"Radu Mateescu, Emilie Oudot","doi":"10.1109/MEMCOD.2008.4547690","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547690","url":null,"abstract":"Equivalence checking is a classical verification method determining if a finite-state concurrent system (protocol) satisfies its desired external behaviour (service) by comparing their underlying labeled transition systems (LTSs) modulo an appropriate equivalence relation. Local (or on-the- fly) equivalence checking explores the synchronous product of the LTSs incrementally, allowing an efficient detection of errors in complex systems. In this paper, we consider the technique based on translating the equivalence checking problem in terms of the local resolution of a Boolean equation system (BES). We propose two enhancements of this technique in the case of equivalent LTSs: a new, faster BES encoding of weak equivalence relations, and a new local BES resolution algorithm with a good average complexity. These enhancements were incorporated into the BISIMULATOR 2.0 equivalence checker of the CADP toolbox, and led to significant performance improvements.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126042918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study 基于Pentium的RTL抽象系统Verilog重写系统
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547693
S. Haynal, T. Kam, M. Kishinevsky, Emily J. Shriver, Xinning Wang
{"title":"A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study","authors":"S. Haynal, T. Kam, M. Kishinevsky, Emily J. Shriver, Xinning Wang","doi":"10.1109/MEMCOD.2008.4547693","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547693","url":null,"abstract":"This paper presents a new tool for SystemVerilog RTL modifications with on-the-fly validation of local RTL changes. The tool, SV-rewrite, imports an initial version of SystemVerilog RTL and elaborates it into a hierarchical design description visualized as structural diagrams. From the design cockpit the user can select any set of visualized components, open a favorite text editor, modify then validate the new RTL description, and finally substitute this new rewritten RTL into the larger model to replace the originally selected components. This process of local validated rewrites can be repeated until the entire RTL is safely rewritten. We studied RTL abstraction using SV-rewrite to abstract the Pentium 80602 (P54CS) integer execution unit and register file. We have produced a significantly more readable RTL that is 2 to 3 times smaller than the original one. The abstracted RTL was validated by booting Linux on an FPGA-based emulation platform.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131988657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Programming Multicores with Kahn Process Networks; a Smart Choice? 基于Kahn进程网络的多核编程明智的选择?
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547679
B. Kienhuis
{"title":"Programming Multicores with Kahn Process Networks; a Smart Choice?","authors":"B. Kienhuis","doi":"10.1109/MEMCOD.2008.4547679","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547679","url":null,"abstract":"","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115022202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Specification and Verification of LambdaRAM- A Wide-area Distributed Cache for High Performance Computing 面向高性能计算的广域分布式缓存——LambdaRAM的规范与验证
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547709
V. Vishwanath, L. Zuck, J. Leigh
{"title":"Specification and Verification of LambdaRAM- A Wide-area Distributed Cache for High Performance Computing","authors":"V. Vishwanath, L. Zuck, J. Leigh","doi":"10.1109/MEMCOD.2008.4547709","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547709","url":null,"abstract":"LambdaRAM is a high-performance, multidimensional, wide-area, distributed cache that takes advantage of massively available memory from multiple clusters interconnected by ultra high-speed networking to provide data-intensive scientific applications with rapid access to both local and remote data without suffering the latency bottlenecks often associated with large storage systems and wide-area data access. LambdaRAM has been demonstrated to yield significant performance speed-ups for geophysical and Bioscience applications accessing extremely large datasets. Currently, LambdaRAM is being integrated by NASA for the modelling, analysis and prediction (MAP) program applications to study tropical cyclones. Formal verification o/LambdaRAM is important to NASA to ensure that LambdaRAM operates reliably in real-time mission critical deployments. We present our preliminary steps towards full formal verification of LambdaRAM. We first give an abstract description of the system and then verify several of its properties. Most of the proofs are accomplished by automatic techniques, while some require deductive steps.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126265384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Virtual prototyping AADL architectures in a polychronous model of computation 虚拟样机AADL体系结构的多时计算模型
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547701
Yuexi Ma, J. Talpin, T. Gautier
{"title":"Virtual prototyping AADL architectures in a polychronous model of computation","authors":"Yuexi Ma, J. Talpin, T. Gautier","doi":"10.1109/MEMCOD.2008.4547701","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547701","url":null,"abstract":"While synchrony and asynchrony are two distinct concepts of concurrency theory, effective and formally defined embedded system design methodologies usually mix the best from both synchronous and asynchronous worlds by considering locally synchronous processes composed in a globally asynchronous way to form so called GALS architectures. In the avionics domain, for instance, the Architecture Analysis and Design Language (AADL) may be used to describe both the hardware and software architecture of an application at system-level. Yet, a synchronous design formalism might be preferred to model and validate each of the critical components of the architecture in isolation. In this paper, we illustrate the use of the polychronous (multi-clocked synchronous) paradigm to model partially asynchronous applications. The specification formalism Signal is used to describe real-world avionic applications using concepts of Integrated Modular Avionics (IMA). We show how an AADL architecture can be automatically translated into a synchronous model in SIGNAL using these modeling concepts. We present a case study on the design of generic system architecture. The approach is being implemented in the framework of the ANR project TopCased.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127218822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
MEMOCODE 2008 Co-Design Contest MEMOCODE 2008合作设计竞赛
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547703
P. Schaumont, K. Asanović, J. Hoe
{"title":"MEMOCODE 2008 Co-Design Contest","authors":"P. Schaumont, K. Asanović, J. Hoe","doi":"10.1109/MEMCOD.2008.4547703","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547703","url":null,"abstract":"The second MEMOCODE hardware/software codesign contest invites participants to solve a practical hardware/software codesign problem within the time span of one month. The larger objective for this contest is to be a showcase of advances in co-design tools and methodologies, in combination with design ingenuity and creativity. In the second installment of the contest, we received 9 submissions. In this short writeup, we review this year's design problem, and we consider relevant contest statistics.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125492834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Static Deadlock Detection for the SHIM Concurrent Language SHIM并发语言的静态死锁检测
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547686
N. Vasudevan, S. Edwards
{"title":"Static Deadlock Detection for the SHIM Concurrent Language","authors":"N. Vasudevan, S. Edwards","doi":"10.1109/MEMCOD.2008.4547686","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547686","url":null,"abstract":"Concurrent programming languages are becoming mandatory with the advent of multi-core processors. Two major concerns in any concurrent program are data races and deadlocks. Each are potentially subtle bugs that can be caused by non-deterministic scheduling choices in most concurrent formalisms. As an alternative, the SHIM concurrent language guarantees the absence of data races by eschewing shared memory, but a SHIM program may still deadlock if a program violates a communication protocol. We present a model-checking-based static deadlock detection technique for the SHIM language. Although SHIM is asynchronous, its semantics allow us to model it synchronously without losing precision, greatly reducing the state space that must be explored. This plus the obvious division between control and data in SHIM programs makes it easy to construct concise abstractions. Experimentally, we find our procedure runs in only a few seconds for modest-sized programs, making it practical to use as part of a compilation chain.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Correctness of a Fault-Tolerant Real-Time Scheduler and its Hardware Implementation 一种容错实时调度程序的正确性及其硬件实现
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547708
Eyad Alkassar, P. Böhm, Steffen Knapp
{"title":"Correctness of a Fault-Tolerant Real-Time Scheduler and its Hardware Implementation","authors":"Eyad Alkassar, P. Böhm, Steffen Knapp","doi":"10.1109/MEMCOD.2008.4547708","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547708","url":null,"abstract":"We formalize the correctness of a fault-tolerant scheduler in a time-triggered architecture. Where previous research elaborated on real-time protocol correctness, we extend this work to gate-level hardware. This requires a sophisticated analysis of analog bit-level synchronization and transmission. Our case-study is a concrete automotive bus controller (ABC), inspired by the FlexRay standard. For a set of interconnected ABCs, vulnerable to sudden failure, we prove at gate-level, that all operating ABCs are synchronized tightly enough such that messages are broadcast correctly. This includes formal arguments for startup, failures, and reintegration of nodes at arbitrary times. To the best of our knowledge, this is the first effort tackling fault-tolerant scheduling correctness at gate-level.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"152 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120874196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Arithmetic Circuits Verification without Looking for Internal Equivalences 不寻找内部等价的算术电路验证
2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547681
O. Sarbishei, B. Alizadeh, M. Fujita
{"title":"Arithmetic Circuits Verification without Looking for Internal Equivalences","authors":"O. Sarbishei, B. Alizadeh, M. Fujita","doi":"10.1109/MEMCOD.2008.4547681","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547681","url":null,"abstract":"In this paper, we propose a novel approach to extract a network of half adders from the gate-level net-list of an addition circuit while no internal equivalences exist. The technique begins with a gate-level net-list and tries to map it into word-level adders based on an efficient bit-level adder representation. It will be shown that the proposed technique is suitable for several gate-level architectures of multipliers, as it extracts adder components in a step-wise method. This approach can also be generalized to other arithmetic circuits. In order to evaluate the effectiveness of our approach, we run it on several arithmetic circuits and compare experimental results with those of contemporary techniques.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127371330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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