2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design最新文献_第3页

A Comparison of Two SystemC/TLM Semantics for Formal Verification 两种用于形式验证的SystemC/TLM语义的比较

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547687

C. Helmstetter, Olivier Ponsini

引用次数: 21

Hands-on Introduction to Bluespec System Verilog (BSV) Bluespec System Verilog (BSV)的实践介绍

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547713

Arvind, R. Nikhil

{"title":"Hands-on Introduction to Bluespec System Verilog (BSV)","authors":"Arvind, R. Nikhil","doi":"10.1109/MEMCOD.2008.4547713","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547713","url":null,"abstract":"BSV is a modern, fully synthesizable design language in which all behavior is expressed with Guarded Atomic Actions (rewrite rules). Rules can be systematically composed from fragments across module boundaries using atomic transactional interfaces. BSV has powerful abstraction mechanisms such as expressive and polymorphic types with overloading and strong static type-checking, full orthogonality (all types are first-class), and Turing-complete static elaboration. Thus, BSV is scalable to large, industrial-strength SoCs even while designs remain highly parameterized and succinct. In this tutorial, you will get a solid technical introduction to BSV and learn how it improves many aspects of modern SoC development: modeling, early SW development, architecture exploration, design, verification, and long-term evolution and maintenance. The lectures will be organized around a few serious examples and we will examine and analyze excerpts of their actual source code. The tutorial is also hands-on: Participants who bring their laptops will receive a non-commercial but full-featured short-term installation of the latest release of BSV (native under Linux, and via a VMWare image for other OSs). During the tutorial you will work with lab exercises tied to the lecture content. After the tutorial you will be able to continue your own exploration with plenty of other examples and lab exercises.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132165243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Estimating the Performance of Cache Replacement Policies 评估Cache替换策略的性能

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547695

Daniel Grund, J. Reineke

{"title":"Estimating the Performance of Cache Replacement Policies","authors":"Daniel Grund, J. Reineke","doi":"10.1109/MEMCOD.2008.4547695","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547695","url":null,"abstract":"Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. The cache performance strongly influences a system's overall performance, as this gap is large and ever-increasing. The efficiency of a given cache architecture - usually measured by its miss ratio - varies greatly depending on the software being executed. We present an efficient method to estimate the miss ratio using a stochastic model. The model takes into account the parameters of the cache architecture and a concise characterization of the software's locality. In contrast to previous approaches, we consider the replacement policy as an important component of the cache architecture. To this end, we introduce policy tables as a concise representation of replacement policies. The software 's locality is characterized by stack histograms or our extension thereof: History stack histograms, which refine stack histograms by distinguishing contexts of accesses. Simulation results on the SPEC benchmarks demonstrate the strong influence of the replacement policy on the miss ratio and the precision of our estimates: average absolute errors between 0.18% and 2.92%.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130587516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications 从多时间规范看确定性多线程软件综合

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI: 10.1109/MEMCOD.2008.4547700

B. Jose, S. Shukla, Hiren D. Patel, J. Talpin

{"title":"On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications","authors":"B. Jose, S. Shukla, Hiren D. Patel, J. Talpin","doi":"10.1109/MEMCOD.2008.4547700","DOIUrl":"https://doi.org/10.1109/MEMCOD.2008.4547700","url":null,"abstract":"In order to exploit the emerging multi-core processors, creating multi-threaded applications is going to be a necessity. However, resolving concurrency, synchronization, and coordination issues, and tackling the non-determinism germane in multi-threaded software is extremely difficult. Ensuring deterministic behavior and correctness with respect to the specification is necessary for safe execution of such code. It is desirable to synthesize multi-threaded code from formal specifications using a provably 'correct-by- construction' approach. In the past, reasonable success has been achieved in the 'correct-by-construction' sequential software synthesis for embedded reactive systems from synchronous programming models. Here we target deterministic multi-threaded software synthesis from deterministic specifications, such that the behavior of the code is semantically equivalent to that of the specification. We choose the polychronous model of computation for specification because (i) such specifications are multi-rate, reactive, concurrent and can be made deterministic through constraints on the environment, and (ii) formal verification methodologies and tools exist for such specifications. In this paper, we analyze under what condition a polychronous specification can be synthesized into multi-threaded C-code preserving its semantics. We also discuss how the synchronous data flow graph structure for a polychronous specification can be used to infer the threading structure of the resulting C-code.","PeriodicalId":221804,"journal":{"name":"2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114584235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16