Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design Contest

Abstract

This paper describes the hardware accelerated crypto sorter design submission for the MEMOCODE 2008 HW/SW co-design contest. The goal was to sort an encrypted database of records partitioning the problem between a PowerPC processor and the dedicated hardware resources available on a Xilinx Virtex II Pro FPGA. A speedup between 24 and 40 was achieved, when compared with the reference software only solution.