硬件加速加密合并排序:MEMOCODE 2008设计竞赛

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design Pub Date : 2008-06-05 DOI:10.1109/MEMCOD.2008.4547705

VJ Sananda

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引用次数: 1

摘要

本文描述了为MEMOCODE 2008硬件/软件协同设计竞赛提交的硬件加速密码分类器设计。目标是对加密的记录数据库进行排序，在PowerPC处理器和Xilinx Virtex II Pro FPGA上可用的专用硬件资源之间对问题进行分区。与仅使用参考软件的解决方案相比，实现了24到40之间的加速。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design Contest

This paper describes the hardware accelerated crypto sorter design submission for the MEMOCODE 2008 HW/SW co-design contest. The goal was to sort an encrypted database of records partitioning the problem between a PowerPC processor and the dedicated hardware resources available on a Xilinx Virtex II Pro FPGA. A speedup between 24 and 40 was achieved, when compared with the reference software only solution.

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2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design

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