Latency-Insensitive Hardware/Software Interfaces

Abstract

Modern embedded system designers face challenges of unprecedented scales, creating systems that integrate functionality spanning disparate scientific domains, with increasing computation demands and ever-stricter power requirements. Meeting the constraints of these systems requires practical design flows that reduce development time without sacrificing design efficiency. Novel design description methodologies coupled with automated and semi-automated synthesis paths greatly accelerate the design of modern hardware systems. In the software space, however, synthesis methods are far from producing co-designs with the necessary efficiency. This is particularly evident at the hardware/software boundary, where the tight coupling of low-level firmware routines and hardware protocols require designers to have deep design knowledge in both domains. To address this issue, we propose a latency-insensitive software execution model that allows direct connection to elastic hardware control topologies.