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2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)最新文献

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Hybrid Beamforming Architecture and Wide Bandwidth True-Time Delay for Future High Speed Communications 5G and Beyond 5G Beamforming System 未来高速通信5G及5G以上波束形成系统的混合波束形成架构和宽带实时延迟
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596451
Ki-Jin Kim, Jae Hong Kang, Ji-Hae Hwang, K. Ahn
{"title":"Hybrid Beamforming Architecture and Wide Bandwidth True-Time Delay for Future High Speed Communications 5G and Beyond 5G Beamforming System","authors":"Ki-Jin Kim, Jae Hong Kang, Ji-Hae Hwang, K. Ahn","doi":"10.1109/ICAM.2018.8596451","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596451","url":null,"abstract":"Multi Antenna systems such as beamforming and MIMO are anticipated to play a key role in 5G and beyond 5G communications. The Phased Array Antennas(PAAs) with phase shifter is the dominant method to achieve beamforming up to now. However the operation bandwidth of PAAs is limited to narrow(~200MHz) due to beam-squint problem. In beyond 5G, hundreds of Gbps data rate are required so the traditional PAAs based beamforming will face technical difficulties in the future. In this paper we proposed new beamforming architecture and an analog True-time delay(TTD) circuit which covers 4.8 GHz bandwidth. The architecture is a combination of phase shifters and TTDs. The analog TTD is composed of all-pass filter based cascade delay cells. The experimentally demonstrated TTD can support 590 psec total-delays with 40 psec resolution which covers more than 1024 number of array in mm-wave 5G system. The measured delay variance is within 4.09 % over the whole operating bandwidth. As a result the proposed scheme is a good candidate for large array and wide width beamforming system.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121731669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 108-dB SNDR 2–1 MASH $DeltaSigma$ Modulator with First-Stage Multibit for Audio Application 108-dB SNDR 2-1 MASH $DeltaSigma$带一级多比特的音频应用调制器
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596380
Yuxiang Tang, Xiaofei Chen, Hongbo Zhu
{"title":"A 108-dB SNDR 2–1 MASH $DeltaSigma$ Modulator with First-Stage Multibit for Audio Application","authors":"Yuxiang Tang, Xiaofei Chen, Hongbo Zhu","doi":"10.1109/ICAM.2018.8596380","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596380","url":null,"abstract":"This paper presents a 108dB SNDR 2–1 MASH switched-capacitor $Delta Sigma$ modulator in standard $0.18mu mathrm{m}$ CMOS technology. The Silva-Steensgaard structure and 4-level quantizer are adopted in the first stage of a 2–1 multistage noise shaping (MASH) topology, which ensure modulator's stability, sufficient noise shaping and power efficiency. Meanwhile, modulator coefficients are optimized for low power consumption. Also, the 4-level quantizer reduces the inherent noise leakage in the MASH $Delta Sigma$ modulator. The data weighted average (DWA) technology in high power efficiency is implemented to address the nonlinearities caused by mismatch among the feedback DAC unit elements. Chopper stabilization (CHS) and bootstrapped switch are implemented to respectively reduce $1/f$ noise and harmonic distortion. Simulation results show that for an oversampling ratio (OSR) of 100, this modulator achieves a peak SNR of 108.88dB, a peak SNDR of 108.02dB and a Schreier FoM of 173.78dB based on SNDR with a 22.05kHz bandwidth.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126271784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10 GS/s, 3-Bit ADC with Novel Decoder in SiGe BiCMOS Technology 采用SiGe BiCMOS技术的10gs /s、3位ADC和新型解码器
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596360
Yuan-Ying Shen, Yi Zhang, Lei Yang, Yanhui Yang, Yu-feng Guo, Xiaopeng Li, Youtao Zhang
{"title":"A 10 GS/s, 3-Bit ADC with Novel Decoder in SiGe BiCMOS Technology","authors":"Yuan-Ying Shen, Yi Zhang, Lei Yang, Yanhui Yang, Yu-feng Guo, Xiaopeng Li, Youtao Zhang","doi":"10.1109/ICAM.2018.8596360","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596360","url":null,"abstract":"This paper presents a design of 10-GS/s, 3-bit analog-to-digital converter in a $mathbf{0.13} mumathbf{m}$ SiGe BiCMOS technology for optical communication application. This fully differential flash ADC includes a wide-bandwidth track-and-hold amplifier, a high-resolution comparator array and a novel differential decoder. By using our novel differential decoder, this ADC design achieves better than 2.8 effective bits for lower input frequencies and 2.5 effective bits for 1 GHz input frequency at a sampling rate of 10 GS/s. This ADC consumes 1.6 W with a 10 GS/s clock rate, while operating from −5/-3.3 V power supplies and its core area is only occupies $mathbf{1}times mathbf{1.2} mathbf{mm}^{2}$.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128341467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Realization of System Verification Platform of IoT Smart Node Chip 物联网智能节点芯片系统验证平台的实现
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596641
Qiming Luo, Ang Lv, L. Hou, Zhongchao Wang
{"title":"Realization of System Verification Platform of IoT Smart Node Chip","authors":"Qiming Luo, Ang Lv, L. Hou, Zhongchao Wang","doi":"10.1109/ICAM.2018.8596641","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596641","url":null,"abstract":"With the development of large scale integrated circuits, the functions of the IoT chips have been increasingly perfect. The verification work has become one of the most important aspects. On the one hand, an efficient verification platform can ensure the correctness of the design. On the other hand, it can shorten the chip design cycle and reduce the design cost. In this paper, based on a transmission protocol of the IoT node, we propose a verification method which combines simulation verification and FPGA-based prototype verification. We also constructed a system verification platform for the IoT smart node chip combining two kinds of verification above. We have simulated and verificatied the related functions of the node chip using this platform successfully. It has a great reference value.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134190400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Error Compensation Methods for Laser-Displacement-Sensors Surface Modeling 激光位移传感器表面建模误差补偿方法
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596331
Haichen Guo, Boyan Zhou, Pingping Yang, Xincheng Gu
{"title":"Error Compensation Methods for Laser-Displacement-Sensors Surface Modeling","authors":"Haichen Guo, Boyan Zhou, Pingping Yang, Xincheng Gu","doi":"10.1109/ICAM.2018.8596331","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596331","url":null,"abstract":"Laser displacement sensors (LDSs) have been widely used in surface modeling for their pinpoint accuracy. To match the high accuracy of LDSs, the influence of machinery vibration must be compensated. In this letter, we built a mathematical model of the relative position between LDSs and objects. Based on the model, the Direct Compensation Method and the Curve Fitting Compensation Method were introduced to separate vibration components from original data for both part-known and completely unknown surfaces. A key and an inner face of a barrel were chosen for the verifications. Both methods were found compensating vibrations well.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132339296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of Low-Power Bandgap Voltage Reference for IoT RFID Communication 物联网RFID通信低功耗带隙电压基准的设计
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596364
Kun Peng, Yong Xu
{"title":"Design of Low-Power Bandgap Voltage Reference for IoT RFID Communication","authors":"Kun Peng, Yong Xu","doi":"10.1109/ICAM.2018.8596364","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596364","url":null,"abstract":"The reference voltage is a core part of RFID tags, its performance directly determines the whole chip's life and performance. The temperature coefficient is one of the important performances of the reference voltage source and the high-order temperature compensation is an effective method to reduce the temperature coefficient of the reference source. A low temperature coefficient bandgap reference is designed based on the standard 65nm CMOS process, and the low-supply voltage operation with bandgap reference circuit with current mode structure. The designed CMOS bandgap voltage reference is in the range of −20°C to 100°C with temperature coefficient of 9.6 ppm/°C and provides a good Power Supply Rejection Ratio(PSRR) of 79dB in the low frequency. The results of simulation show that the design improve the performance of the bandgap reference voltage source effectively.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114238472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An Active Inductor Based Quadrature Voltage-Controlled Oscillator in $mathbf{0.13}mumathbf{m}$ CMOS 基于有源电感的$mathbf{0.13}mumathbf{m}$ CMOS正交压控振荡器
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596537
Ting Ma, Feng Hu
{"title":"An Active Inductor Based Quadrature Voltage-Controlled Oscillator in $mathbf{0.13}mumathbf{m}$ CMOS","authors":"Ting Ma, Feng Hu","doi":"10.1109/ICAM.2018.8596537","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596537","url":null,"abstract":"The design and measurement of a voltage controlled oscillator with quadrature outputs using a CMOS active inductor is presented. The coarse tuning of the quadrature VCO (QVCO) is accomplished through bias current tuning and varactors are added for fine tuning. The oscillator facilitates two working states. When supplied with 1.2 V supply voltage, the tuning range is 1–2 GHz and the phase noise (PN) varies from −71 dBc to −110 dBc at a 1 MHz offset from the carrier frequency. When the QVCO is supplied with 1 V supply voltage, the frequency tuning range is 0.7-1.5 GHz and the measured phase noise is from −71 dBc to −102 dBc at a 1 MHz offset. The output power varies less than 2 dB along all working conditions. The QVCO occupies an area less than 0.015 mm2. Except the output buffer, it consumes 2.5-2.7 mA from 1 V supply and 6.4-7 mA from 1.2 V supply.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116769158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Research and Design of Extended Permutation Module for RISC Processor RISC处理器扩展排列模块的研究与设计
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596378
Lin Chen, Z. Dai, Yuqian Xue, Pengfei Hou
{"title":"Research and Design of Extended Permutation Module for RISC Processor","authors":"Lin Chen, Z. Dai, Yuqian Xue, Pengfei Hou","doi":"10.1109/ICAM.2018.8596378","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596378","url":null,"abstract":"Based on the butterfly network, extended permutation module is designed in this paper. Effectively reducing the hardware area by using the same circuit structure to implement arbitrary permutation and multi-width shift operation. At the same time, the transposition instruction is designed for RISC processor, so it has better practical value. In the case of area and delay only increasing by 25.6% and 13.1%, the unit implements a variety of width rotation shift, logical shift and arithmetic shift, and permutation operation of width extensible, which has high application value in cryptography, digital image processing and other fields.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134525854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Predicting Protein Functions of Bacteria Genomes via Multi-instance Multi-Label Active Learning 基于多实例多标签主动学习的细菌基因组蛋白质功能预测
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596617
Jiansheng Wu, Wenyong Zhu, Y. Jiang, Guwei Sun, Yusheng Gao
{"title":"Predicting Protein Functions of Bacteria Genomes via Multi-instance Multi-Label Active Learning","authors":"Jiansheng Wu, Wenyong Zhu, Y. Jiang, Guwei Sun, Yusheng Gao","doi":"10.1109/ICAM.2018.8596617","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596617","url":null,"abstract":"Bacteria are workhorses in the fields of molecular biology, genetics, and biochemistry. Understanding the biological functions of proteins is important for bacteria studies in the post-genomic era. There are a large number of proteins with unknown biological functions in newly discovered bacteria species. Active learning can assist biologists in selecting the most valuable proteins as candidates for assays. Previously, we formulated the protein function prediction problem as a multi-instance multi-label (MIML) learning task. Here, we propose a MIML active learning algorithm MIMLAL-R for protein function annotation of bacteria genomes. MIMLAL-R minimizes an approximated surrogate loss by stochastic gradient descent with the most valuable bag-label pairs, which are chosen by a selection criterion that combines label cardinality inconsistency and diversity. We tested MIMLAL-R on four real bacteria, namely Geobacter sulfurreducens, Azotobacter vinelandii, Shewanella loihica PV-4, and Escherichia coli strain K12. The MIMLAL-R approach achieved excellent performances in all cases. The codes and data can be freely downloaded from.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123626280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of Reliability Test Device for SPI Interface ReRAM Memory SPI接口存储器可靠性测试装置的设计
2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM) Pub Date : 2018-11-01 DOI: 10.1109/ICAM.2018.8596518
Wang He, Yu Qingkui, Sun Yi
{"title":"Design of Reliability Test Device for SPI Interface ReRAM Memory","authors":"Wang He, Yu Qingkui, Sun Yi","doi":"10.1109/ICAM.2018.8596518","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596518","url":null,"abstract":"This paper designs a reliability test device for Fujitsu 4Mbit SPI interface ReRAM memory. The device uses FPGA as the lower computer controller to realize the basic data writing and reading operation of the SPI interface ReRAM memory. The upper computer software supports the programmable instrument control, the data writing and reading function test of the ReRAM memory, the SEU detection under the continuous reading operation, the continuous writing and reading function test of the specified address. It can be used for the reliability test of SEE, data retention and endurance of ReRAM memory. In the SEE sensitivity test, it is found that the device is prone to SEFI under heavy ion irradiation. After stopping the beam and restarting the system, the data of the ReRAM storage unit has not changed, which proves that the SEU of the data storage unit array has not occurred.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122019733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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