Design of Reliability Test Device for SPI Interface ReRAM Memory

Abstract

This paper designs a reliability test device for Fujitsu 4Mbit SPI interface ReRAM memory. The device uses FPGA as the lower computer controller to realize the basic data writing and reading operation of the SPI interface ReRAM memory. The upper computer software supports the programmable instrument control, the data writing and reading function test of the ReRAM memory, the SEU detection under the continuous reading operation, the continuous writing and reading function test of the specified address. It can be used for the reliability test of SEE, data retention and endurance of ReRAM memory. In the SEE sensitivity test, it is found that the device is prone to SEFI under heavy ion irradiation. After stopping the beam and restarting the system, the data of the ReRAM storage unit has not changed, which proves that the SEU of the data storage unit array has not occurred.