{"title":"A 1-V 90.3-dB DR 100-kHz BW 4th-Order Single Bit Sigma-Delta Modulator in 40-nm CMOS Technology","authors":"Xiao Chen, Zhigong Wang, Fei Li","doi":"10.1109/ICAM.2018.8596548","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596548","url":null,"abstract":"A 1-V 4th-order discrete-time single bit sigma-delta modulator over a signal bandwidth of 100 kHz is presented in this paper. The feed forward topology is selected to reduce the voltage swings of the integrators. In addition, a novel two-stage inverter-based amplifier is proposed to improve the DC gain in low voltage environment. To save power consumption, a pure dynamic comparator is employed. Designed and implemented in 40-nm CMOS technology, the modulator achieves 88.5 dB peak SNDR (signal-to-noise and distortion ratio) and 90.3 dB DR (dynamic range). The core area of the chip is 0.133 mm2 and the total power consumption is 1 mW.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124831219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parallel Integrated State Variable Filter Circuit Design","authors":"J. Ren, Fuqiang Wang, Rui Min, Xiao-ning Xin","doi":"10.1109/ICAM.2018.8596415","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596415","url":null,"abstract":"In this paper, a parallel state variable filter circuit is designed. The integrated operational amplifier is used as the amplifying circuit. The state variable method is used to solve the differential equation to realize the high-pass, low-pass and band-pass band-stop filtering functions of parallel filtering. Through the Cadence software simulation, the state variable filter high-pass circuit cut-off frequency is 32.9KHz, the low-pass circuit cut-off frequency is 1.7KHz, the band-pass circuit center frequency is 7.0KHz, the band-stop circuit center frequency is 7.0KHz. The quality factor of the filter is 0.2, which is significantly better than other designs under the same conditions. Finally, the circuit layout is drawn using Cadence software. In this paper, the circuit simulation, layout drawing and verification are carried out with Virtuso, Spectre and Caliber software integrated in the Cadence system.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122311167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems","authors":"","doi":"10.1109/icam.2018.8596635","DOIUrl":"https://doi.org/10.1109/icam.2018.8596635","url":null,"abstract":"","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132250107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"OMAPL138 Based Image Acquisition and Display System Development","authors":"Yangqing Sun, Y. Hua","doi":"10.1109/ICAM.2018.8596541","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596541","url":null,"abstract":"An OMAPL38 based high sensitive CMOS image acquisition and display system has been developed. This system is designed for iris recognition which requires high speed and high sensitive raw images. The image size of the system is $752times 480$ (10bit) and the experimental results indicate that the readout speed exceeds 60fps with the peak quantum efficiency over 50%. This system opens new possibilities for the real-time biometric matching of eye images. The hardware and software details are described in this paper.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132030429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yong Yang, Lin Zhao, Junping Cao, Hang Jiang, Shaohua Wang, Luyao Zhou
{"title":"Influence of Cable Terminal Floating Potential Defect on Electric Field","authors":"Yong Yang, Lin Zhao, Junping Cao, Hang Jiang, Shaohua Wang, Luyao Zhou","doi":"10.1109/ICAM.2018.8596569","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596569","url":null,"abstract":"To research the influence of floating potential defect on electric field distribution, an electric field simulation software applying the finite element method was adopted to establish a simulation model for computing the electric field distribution around the cable terminal. The influence of different lengths of defects on the maximum electric field are analyzed. Oscillation wave partial discharge test system was established. The results show that the maximum electric field intensity of the defect area increases with the increasing of the length of the metal plate first, then decreases, and finally increases. The maximum electric field intensity increases linearly with the changing of the cable core voltage, and the maximum electric field value exceeds the design value. Oscillatory wave test results show that floating potential defect can easily make electric field aberrant and lead to significant PD phenomenon, verifying that the electric field simulation result is correct.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116699754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"All-Digital Delta-Sigma TDC with Differential Multipath Pre-Skewed Gated Delay Line Time Integrator","authors":"F. Yuan, Parth Parekh","doi":"10.1109/ICAM.2018.8596506","DOIUrl":"https://doi.org/10.1109/ICAM.2018.8596506","url":null,"abstract":"This paper presents an all-digital 1st-order 1-bit delta-sigma time-to-digital converter ($Delta Sigma$ TDC) with a differential multipath pre-skewed bi-directional gated delay line (BDGDL) time integrator. Differential time integration is obtained by performing simultaneous left-shift and right-shift operations of the BDGDL. Pre-skewing is used to lower the per-stage delay and skew error of BDGDL. The time integrator features low power consumption accredited to the use of only one BDGDL to perform differential time integration, rapid time integration, full compatibility with technology, and built-in digitization. The TDC was designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. A sinusoidal time input of 333 ps amplitude and 244 kHz frequency is digitized by the TDC. Simulation results show the TDC provides 39.7 dB SNDR, 6.5 ENOB, and 3.7 ps time resolution over frequency range from flicker noise corner frequency 32 kHz to 3rd harmonic frequency 732 kHz while consuming $407 mu mathrm{W}$. The FOM of the TDC is 3.2 Pj/step, outperforming that of reported TDCs alike.","PeriodicalId":220324,"journal":{"name":"2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121766967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}